Silicon Physical Design Engineer

Google Inc.; Sunnyvale (CA); On-site; USD 116,000 - 166,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google Inc. in Sunnyvale, CA seeks a Physical Design Engineer to contribute to TPU chip blocks from RTL to GDS and push PPA boundaries.

You will collaborate with RTL/Design and PD teams to optimize runs, conduct feasibility studies for new microarchitectures, and promote high QoR. Strong knowledge of EDA flows and STA is required, with scripting experience valued.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 1 year of experience with physical design.
• Experience with scripting languages (Perl, Python, Tcl).
• Experience with Synopsys/Cadence PnR tools and backend flows (LEC/PI-SI/DRC-LVS).
• Experience in static timing analysis (STA) and defining timing corners, margins, and derates.

Responsibilities

• Participate in the Physical Design (PD) of blocks for complex TPU chips.
• Contribute to the design and closure of the subchip and individual blocks RTL-to-GDS.
• Collaborate with RTL/Design and PD teams to optimize PPA and QoR.
• Create and maintain silicon deliverables documentation to promote efficiency and sustainability.
• Identify test requirements, select appropriate tools, and test Silicon systems.

Skills

Physical design

Scripting Perl

Scripting Python

Scripting Tcl

PD tools (Synopsys/Cadence)

Backend flows (LEC, PI/SI, DRC/LVS)

Static timing analysis (STA)

Education

Bachelor's degree in Electrical Engineering/Computer Engineering/Computer Science or related field

Job description

Google – Physical Design Engineer, Sunnyvale, CA, USA

Required qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 1 year of experience with physical design.
• Experience with scripting languages such as Perl, Python, or Tcl.
• Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
• Experience in static timing analysis (STA), including experience defining timing corners, margins, and derates.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with constraints, synthesis or clock tree synthesis (CTS).
• Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design.
• Experience working with external partners on physical design (PD) closure.
• Understanding of DFT including Scan, MBIST and LBIST.
• Understanding of performance, power and area (PPA) trade-offs.

Responsibilities

• Participate in the Physical Design (PD) of blocks for complex TPU chips.
• Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS.
• Collaborate with RTL/Design and PD teams to achieve the best PPA possible, including conducting feasibility studies for new microarchitectures as well as optimizing runs for best Quality of Results (QoR).
• Create and maintain policies, processes, procedures, methods, tests, and documentation of silicon deliverables for the purpose of enhancing and promoting high efficiency, productivity, and sustainability.
• Identify test requirements, select appropriate tools, methods, and approach, and carry out testing of Silicon systems, influence designs to enable and enhance testing, validation, and debugging.

Benefits

• US: $116000 - $166000 (USD) + 15% bonus target + equity + benefits

English Proficiency

English proficiency is a requirement for all roles unless stated otherwise in the job posting.

EEO Statement

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.