CPU Physical Design Automation & Infrastructure Engineer

QUALCOMM, Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 148,000 - 222,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking an experienced CPU Physical Design Infrastructure and Automation Engineer to drive infrastructure improvements and automation for next‑generation CPUs.

You will collaborate with PD, CAD, Methodology, and STA teams to enable scalable design infrastructure and predictive timing models. The role emphasizes development of dashboards, data‑driven bottleneck analysis, and automation to accelerate timing, power, and area estimations across

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• MS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; 10 years of practical experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Responsibilities

• Work with cross functional teams (PD, CAD, Methodology and STA) to bring up design infrastructure and dashboards for multiple CPU designs and domains.
• Work with all block level implementation teams to analyze, implement and improve the optimization method as it pertains to the designs.
• Work on developing new prediction models and automation for quick timing, power and area estimation.

Skills

Synthesis

Place & Route

Signoff timing/power analysis

Scripting

Data analytics

Programming

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

MS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synthesis tools

Place & Route tools

STA tools

Design signoff tools

Job description

Qualcomm Technologies, Inc. in Santa Clara, CA is seeking an experienced CPU Physical Design Infrastructure and Automation Engineer to drive infrastructure improvements and automation for next‑generation CPUs.

You will collaborate with PD, CAD, Methodology, and STA teams to enable scalable design infrastructure and predictive timing models. The role emphasizes development of dashboards, data‑driven bottleneck analysis, and automation to accelerate timing, power, and area estimations across