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Qualcomm in Santa Clara, CA is seeking a Physical Design Clock Engineer to collaborate with microarchitecture, RTL, CAD, block and top-level physical design teams to create best-in-class clocking solutions for next generation CPUs.
The role requires expertise in clock generation, jitter analysis, and low-skew/low-power design, with responsibilities spanning PLLs, CTS, and clock distribution methodology across CPU designs.
We are seeking a Physical Design Clock Engineer to work with microarchitecture, RTL design, CAD, block level and top level physical design teams to create best in class clocking solutions for next generation CPUs.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Pay range: $142,200.00 - $213,400.00. Competitive annual discretionary bonus program, opportunity for annual RSU grants.
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process and will provide reasonable accommodations to support participation in the hiring process.