Senior CPU Clock Design & Distribution Engineer

NUVACORE; Austin (TX); On-site; USD 140,000 - 230,000; Full time

Job summary

NUVACORE is building high-performance, low-power CPUs. As a Custom Clock Design and Distribution (CCD) Engineer, you will architect the clock generation and distribution networks that set frequency, skew, jitter, and power budgets for upcoming cores.

You will work across PLL/FLL, timing, CAD, physical design, and DFT teams to deliver clock networks from architecture to tape-out, leveraging transistor-level clock circuits and rigorous SPICE analysis to meet PPA targets.

Qualifications

• 5+ years clock design/distribution experience.
• Transistor-level design with dividers, deskew, duty-cycle correction, clock-gating.
• Proven low-skew, low-power clock networks using CTS for high-frequency CPUs.
• Strong SPICE analytics and signal integrity knowledge for clock paths.
• STA/clock timing signoff across Functional and DFT modes.
• Track record delivering clock networks through tape-out with PPA data.

Responsibilities

• Architect and drive end-to-end clock generation and distribution methodology.
• Design and characterize clock circuits at transistor level.
• Own end-to-end clock-network closure: SPICE, EM/IR, and STA signoff.
• Partner with PLL/FLL, timing, CAD, physical design, and DFT teams.

Skills

Clock design

SPICE simulation

Signal integrity

Team collaboration

Automation scripting

Foundry collaboration

Education

BS or MS in Electrical Engineering

Tools

SPICE

Python

Perl

TCL

Job description

NUVACORE is building high-performance, low-power CPUs. As a Custom Clock Design and Distribution (CCD) Engineer, you will architect the clock generation and distribution networks that set frequency, skew, jitter, and power budgets for upcoming cores.

You will work across PLL/FLL, timing, CAD, physical design, and DFT teams to deliver clock networks from architecture to tape-out, leveraging transistor-level clock circuits and rigorous SPICE analysis to meet PPA targets.