Senior CPU Clock Architect – Distribution & Signoff

NUVACORE

Santa Clara (CA)

On-site

USD 180,000 - 260,000

Full time

2 days ago

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Job summary

Nuvacore in Santa Clara, CA is seeking a Custom Clock Design and Distribution (CCD) Engineer to lead end-to-end clock networks for high-frequency CPUs. You will architect clock generation using H-tree, mesh, and multi-source CTS, drive PPA across PVT, and collaborate with PLL, CAD, physical design, and DFT teams to optimize skew, jitter, and power.

Ideal candidates have 5+ years of hands-on transistor-level clock design, proficiency in SPICE, and strong programming in Python/Perl/TCL.

Qualifications

BS or MS degree with 5+ years of clock-design experience for IC roles; 12+ years for Lead roles.
Hands-on transistor-level clock design with dividers, deskew, duty-cycle correction, clock-gating and mux cells.
Proven track record building low-skew, low-power clock networks for high-frequency CPUs.
Strong SPICE, device physics, RC delay and signal integrity knowledge for clock paths.

Responsibilities

Architect end-to-end clock-generation and distribution for high-frequency CPU cores.
Design clock circuits at transistor level, including buffers, dividers, deskew and gating cells.
Own clock-network signoff: SPICE skew, latency, jitter; ensure EM/IR and timing across Functional/DFT modes.
Collaborate with PLL/FLL, timing, power, CAD, physical design and DFT teams on clock models and budgets.