Contract Verification Engineer — SV/UVM Expert

Wipro Technologies; Santa Clara (CA); On-site; USD 60,000 - 149,000; Full time

Job summary

Wipro Limited, a leading technology services and consulting company, is seeking a Verification Engineer for a CONTRACT in California. The role involves building UVM/SystemVerilog based verification environments, developing test plans according to specifications, and debugging RTL with design teams.

Requirements include strong SV and UVM understanding and 5-8 years of experience in VLSI HVL verification. The compensation ranges from $60,000 to $148,500, with standard Wipro benefits and potential

Qualifications

• Mandatory: VLSI HVL verification.

Responsibilities

• Build UVM/SystemVerilog-based verification environments for IP/subsystem/SoC level testing.
• Develop directed and random test cases, perform coverage analysis and close functional/code coverage.
• Debug simulation failures and work with RTL designers to resolve issues.
• Execute regression runs, analyze results, and contribute to process improvements.
• Document test environments, plans and results for reviews.

Skills

VLSI HVL Verification

Job description

Wipro Limited, a leading technology services and consulting company, is seeking a Verification Engineer for a CONTRACT in California. The role involves building UVM/SystemVerilog based verification environments, developing test plans according to specifications, and debugging RTL with design teams.

Requirements include strong SV and UVM understanding and 5-8 years of experience in VLSI HVL verification. The compensation ranges from $60,000 to $148,500, with standard Wipro benefits and potential