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Amazon Web Services in Cupertino, CA is seeking an ASIC Design Engineer to lead high-performance RTL design and optimization for data-center hardware, including SystemVerilog implementation and timing analysis.
You will collaborate with architects, verification, and back-end teams to ensure power-efficient, scalable solutions for AWS ML accelerators and related datacenter infrastructure.
Amazon Web Services in Cupertino, CA is seeking an ASIC Design Engineer to lead high-performance RTL design and optimization for data-center hardware, including SystemVerilog implementation and timing analysis.
You will collaborate with architects, verification, and back-end teams to ensure power-efficient, scalable solutions for AWS ML accelerators and related datacenter infrastructure.