Cloud-Scale ML Inference ASIC Design Engineer

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

A ASIC Design Engineer at Annapurna Labs (U.S.) Inc. in Austin, TX will design high-performance SystemVerilog RTL for data-center silicon, focusing on power efficiency and area optimization. You will collaborate with architects, verification, and back-end teams to deliver timing-clean designs and robust IP.

The role requires a BS in Electrical Engineering or related field, strong debugging skills, and experience across SoCs, IP blocks, and system-level verification. Relocation not specified.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing

Responsibilities

• Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets
• Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints
• Execute lint and clock domain crossing quality checks to ensure design integrity
• Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts

Skills

SystemVerilog RTL

RTL design

Power-aware design

Debugging skills

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Tools

Synthesis tools

Timing analysis

Python

Perl

Job description

A ASIC Design Engineer at Annapurna Labs (U.S.) Inc. in Austin, TX will design high-performance SystemVerilog RTL for data-center silicon, focusing on power efficiency and area optimization. You will collaborate with architects, verification, and back-end teams to deliver timing-clean designs and robust IP.

The role requires a BS in Electrical Engineering or related field, strong debugging skills, and experience across SoCs, IP blocks, and system-level verification. Relocation not specified.