Cloud-Scale ML Acceleration: ASIC Design Engineer

Socket.dev; Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Amazon Web Services is seeking an ASIC Design Engineer to trail-blaze new technologies and architectures for high-performance data-center hardware. You will design SystemVerilog RTL, optimize power and area while meeting tight targets, and collaborate across architecture, verification, and back-end teams.

A strong background in ASIC design and SystemVerilog, plus excellent debugging and problem-solving skills, are essential. Familiarity with RF, accelerator engines, and related subs is a plus.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field is required.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.
• Preferred: Master's degree in Electrical or Communications Engineering or related field.
• Experience with ARM and DSP ISAs; familiarity with RF standards and wireless technologies.

Responsibilities

• Develop high-performance, area and power-efficient RTL designs to meet project specs.
• Analyze designs, microarchitectures, and architectures to optimize trade-offs between features, power, performance and area.
• Create microarchitectures, implement SystemVerilog RTL, deliver synthesis and timing-clean designs with constraints.
• Perform lint and clock-domain crossing checks to ensure design integrity.
• Collaborate with cross-functional teams including architects, verification specialists, and back-end teams.

Skills

Bug identification

SystemVerilog debugging

System verification

ARM DSP ISAs

Python/Perl automation

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical or Communications Engineering

Job description

Amazon Web Services is seeking an ASIC Design Engineer to trail-blaze new technologies and architectures for high-performance data-center hardware. You will design SystemVerilog RTL, optimize power and area while meeting tight targets, and collaborate across architecture, verification, and back-end teams.

A strong background in ASIC design and SystemVerilog, plus excellent debugging and problem-solving skills, are essential. Familiarity with RF, accelerator engines, and related subs is a plus.