Clocks ASIC Engineer: Optimize GPU/CPU Timing & PPA

NVIDIA; United States; Hybrid; USD 116,000 - 219,000; Full time

Job summary

NVIDIA is seeking an ASIC clocking engineer to architect the clock domain for GPUs/CPUs, collaborating with multiple teams to satisfy architectural, physical and validation constraints.

You will drive PPA improvements, implement clocking topologies in RTL, and partner with Physical and timing teams to resolve clocking challenges, delivering RTL to verification and DFT groups for silicon bringup.

Qualifications

• BS in Electrical Engineering or equivalent experience (MS preferred).
• 2+ years of relevant work experience.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability to collaborate with multiple teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in Python or other industry-standard scripting languages.
• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
• Implementing on-chip clocking networks is a bonus.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams to design GPU/CPU clocks meeting architectural and physical constraints.
• Improve Power, Performance, and Area (PPA) by evaluating trade-offs across DFx, physical implementation, and timing closure; develop and implement new clocking topologies in RTL.
• Collaborate with Physical design and timing teams on clocking concerns and solutions for high-speed clocking.
• Deliver clock RTL information to GPU, CPU and SOC verification, timing and DFT teams.
• Participate in end-to-end ASIC execution cycle from micro-arch to silicon bringup.

Skills

Verilog RTL

Python

PPA trade-offs

Cross-team collaboration

Education

BS in Electrical Engineering

Tools

Verilog

Logic Synthesis Tools

Job description

NVIDIA is seeking an ASIC clocking engineer to architect the clock domain for GPUs/CPUs, collaborating with multiple teams to satisfy architectural, physical and validation constraints.

You will drive PPA improvements, implement clocking topologies in RTL, and partner with Physical and timing teams to resolve clocking challenges, delivering RTL to verification and DFT groups for silicon bringup.