Physical Design Lead

Phinity Labs; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health insurance

Retirement plans

Unlimited PTO

Paid parental leave

Lunch and dinner provided in-office

Job summary

Phinity Labs, an AI research lab in San Francisco, seeks a Physical Design Lead to drive block-to-full-chip PD flows and optimize PPA. You will define synthesis-to-layout flows, PDN, clock trees, and cell characterizations, delivering tapeout-ready designs.

You will collaborate with top researchers and hardware experts, shape strategy, and own high-impact PD initiatives across power, performance, and area trade-offs in cutting-edge accelerator chips.

Qualifications

• 5+ years leading physical design in ICs or SOCs.
• Experience delivering tapeout-ready PD designs.
• Strong knowledge of Synthesis, layout, PDN, and clock networks.

Responsibilities

• Lead PD flows and optimization from block to full-chip.
• Define Synthesis to layout flows, including PDN, clock-trees, PVT corners, and custom cells.
• Execute IP and full-chip design optimizations with PD engineers.
• Deliver tapeout-ready designs optimized for target PPA.

Skills

PD flows

Full-chip optimization

Clock trees

Synthesis layout

Tools

ECAD tools

Job description

Phinity is an AI research lab focused on solving chip design. The bottleneck to AGI is compute, and we enable AI agents to tape-out chips autonomously, from architecture to post-silicon. We are building RL environments, agent infrastructure, and evaluation systems to accomplish this. Our team brings together deep AI and silicon expertise, including leaders and executives from top chip companies, post-training chip-design models at NVIDIA, AI for formal verification research, previous exits, and over 10 years of experience building chips at NVIDIA, Intel, Mediatek, and others.

We are hiring a Physical Design Lead.

You will be responsible for:

• Leading PD flows and optimization of block-level to full-chip level optimizations
• Define Synthesis to layout flows, including PDN, clock-trees, PVT corners and custom cell definitions. Responsible for implementing characterization flows for custom cells and memory blocks.
• Responsible for executing IP and Fullchip design optimizations working with PD engineers. Identify areas of optimization in design utilization, power grid and clock network within the design.
• Responsible for delivering tapeout ready design optimized for the target PPA, and utilizing the in-house capability on prompt-to-GDS.

Why Phinity

• Work directly with the founders to shape the strategy and growth of an ambitious AI research lab
• Take ownership of high-impact initiatives across business strategy, partnerships, and company operations
• Collaborate with leading AI researchers and hardware experts at the frontier of autonomous chip design

Benefits include

• Health insurance
• Retirement plans
• Unlimited PTO
• Paid parental leave
• Lunch and dinner provided in-office