ASIC Verification Engineer

Broadcom; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary annual bonus

New hire equity grant

Annual equity awards

401(k) matching

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid sick leave

Paid vacation

Job summary

Broadcom is seeking an ASIC Verification Engineer in Fort Collins, Colorado to design, implement, and maintain verification infrastructure for a diverse ASIC portfolio. In this role, you will collaborate with design teams to develop exhaustive verification plans, construct reusable testbenches, and continuously scale verification coverage to ensure first-pass silicon success.

Key responsibilities include building testbenches with SystemVerilog/UVM, writing coverage-driven tests, and maintaining

Qualifications

• Bachelor's or Master’s degree with required years of ASIC verification experience as specified in the ad.

Responsibilities

• Design and implement verification environments using SystemVerilog and UVM.
• Create reusable components including reference models, checkers, monitors, scoreboards and firmware code.
• Develop verification plans, run constrained-random tests, and debug complex ASIC IP blocks.
• Manage regression runs, triage failures and track coverage and QA.

Skills

SystemVerilog

UVM

Verilog

SVA

C/C++

Python scripting

ARM architecture

AMBA AXI/ABP

DSP reference models

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in related field

Job description

Job Description

Job Title: ASIC Verification Engineer

Job Summary

We are seeking a highly skilled ASIC Verification Engineer to design, implement, and maintain advanced verification infrastructure across our diverse portfolio of ASIC products. In this role, you will collaborate with design teams to develop exhaustive verification plans, construct reusable testbenches, and continuously scale verification coverage to ensure first-pass silicon success.

Key Responsibilities

• Testbench Design & Implementation: Architect and develop robust, scalable, and reusable verification environments using SystemVerilog and UVM. Create modular components including reference models, checkers, monitors, scoreboards, and targeted firmware code.
• Verification Strategy & Execution: Author detailed verification plans by analyzing architectural specs. Develop, execute, and debug directed and constrained-random test cases to validate complex ASIC IP blocks.
• Coverage Closure & Quality Assurance: Track, analyze, and maximize functional and code coverage metrics. Write SystemVerilog Assertions (SVA) to implement assertion-based verification and trap corner-case design bugs.
• Database & Regression Management: Establish, maintain, and optimize operation processes for design database management and official database releases. Oversee automated daily/weekly regression runs, triage failures, and manage performance tracking.

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with a minimum of 8 years of relevant ASIC verification experience.
• OR Master's Degree in a related field with a minimum of 6 years of relevant ASIC verification experience.

Preferred Skillsets & Technical Knowledge

• Languages: Strong proficiency in SystemVerilog, Verilog coding, and SystemVerilog Assertions (SVA).
• Methodologies: Hands-on experience building testbenches from scratch using the Universal Verification Methodology (UVM).
• Flows: Deep understanding of the front-to-back ASIC design and verification lifecycle (pre-silicon simulation, debugging, and coverage closure).
• Architecture & Subsystems: Familiarity with ARM processor architectures and AMBA subsystem protocols (e.g., AXI, AHB, APB).
• Algorithms: Exposure to Digital Signal Processing (DSP) algorithms and translating them into hardware verification reference models.

Software & Scripting:

Strong programming skills in C/C++ and scripting expertise in Python, Perl, or Tcl for environment automation and regression sorting.

Compensation And Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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