Senior ASIC Verification & Methodology Engineer

Nutanix

San Diego (CA)

On-site

USD 140,000 - 210,000

Full time

14 days+

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Benefits offered by this job

RSU grants
Annual bonus
Benefits package

Job summary

Qualcomm Technologies, Inc. is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP/SoC development for high performance, low power products.

You will collaborate with software and hardware teams, evaluate process flows, and use RTL to GDS Flow and Virtuoso to drive architecture and implementation across multiple complex blocks.

Qualifications

  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

  • Leverages advanced ASIC knowledge to define, model, design, optimize, verify, validate, implement, and document IP/SoC development.
  • Creates advanced architectures and circuit specifications based on system-level requirements.
  • Collaborates with cross-functional teams to develop and execute implementation strategies.

Skills

ASIC design
Verification
RTL/Verilog
Scripting
Communication with leadership

Education

Bachelor's degree in Science/Engineering
Master's degree in Science/Engineering
PhD in Science/Engineering

Tools

RTL to GDS Flow
Virtuoso
EDA tools

Job description

Qualcomm Technologies, Inc. is seeking an experienced ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP/SoC development for high performance, low power products.

You will collaborate with software and hardware teams, evaluate process flows, and use RTL to GDS Flow and Virtuoso to drive architecture and implementation across multiple complex blocks.

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