ASIC Verification Architect for High-Performance SoCs

Qualcomm; Santa Clara (CA); On-site; USD 107,000 - 161,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance, low-power products.

Collaborate with cross-functional teams to determine product execution paths and contribute to architecture, design verification methods, and flow optimization across the IP lifecycle.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science preferred.
• 6+ months of experience with architecture and design tools.
• 6+ months of experience with scripting tools and programming languages.
• 6+ months of experience with design verification methods.

Responsibilities

• Applies ASIC knowledge to assist and support IP development across high-performance, low-power products.
• Assists in architectures, circuit specs, logic designs, and system simulations.
• Collaborates to develop implementation strategies meeting system requirements and customer needs.
• Supports evaluation of process flow from high-level design to synthesis, place and route, timing and power use, and verification.

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science

Tools

Architecture & design tools

Scripting & programming languages

Design verification methods

Job description

Qualcomm Technologies, Inc. in Santa Clara seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance, low-power products.

Collaborate with cross-functional teams to determine product execution paths and contribute to architecture, design verification methods, and flow optimization across the IP lifecycle.