Principal ASIC Verification

Tara Technical Solutions (TTS); San Jose (CA); On-site; USD 170,000 - 230,000; Full time

Job summary

Tara Technical Solutions (TTS) seeks a Principal ASIC Verification engineer in San Jose for a direct-hire role with a Fortune 500 client. Lead testbench design, plan verification across Block/Core/SOC, and drive functional coverage to closure.

Ideal candidate brings 12+ years of experience in complex verification environments, full ASIC cycle experience, and strong SystemVerilog/UVM/VMM skills. Collaboration with a senior team and mentoring is expected.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics/Equivalent with related ASIC/verification experience.
• 10+ years in developing complex verification environments, test plans, coverage, and pseudo-random testing.
• Experience leading a core ASIC verification cycle from architecture through tapeout.
• Proficient in SystemVerilog and verification methodologies (UVM/VMM).
• Strong debugging skills for regression failures and understanding complex designs.
• Knowledge of PCI Express or similar multi-layered protocols.

Responsibilities

• Architect and develop scalable testbench environments and reusable verification components.
• Drive test plans for block/core/SOC features and write functional coverage.
• Create pseudo-random tests to achieve full functional coverage and closure.
• Debug regression failures and close coverage gaps by improving tests.
• Mentor junior engineers and guide verification teams.
• Lead documentation of verification strategy and review with design/architectures.
• Improve verification quality and efficiency of the team.

Skills

SystemVerilog

UVM/VMM

ASIC verification

PCI Express protocol

Debug/analysis

Mentoring

Verification methodology

Education

Bachelor’s degree in Electrical/Electronics/Equivalent

Master’s degree in Electrical/Electronics/Equivalent

Tools

Makefiles

Job description

Principal ASIC Verification: San Jose Full-Time Direct Hire with our Fortune 500 Client.

• Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
• Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
• Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
• Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
• Work with other members of the team, guide/mentor junior team members
• Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
• Driver Verification quality and Efficiency improvements.

Mandatory Requirements:

• Bachelor’s degree in Electrical/Electronics/Equivalent with 12+ years of relevant experience; or Master’s degree in Electrical/Electronics/Equivalent with 10+ years of relevant experience
• 10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
• Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification leading a Core
• Very proficient in System Verilog and Verification Methodologies like UVM/VMM
• Good debug skills in analyzing regression failures and understanding of complex designs
• A good understanding of a complex protocol like PCI Express or other multi-layered protocol.

Nice to have NOT a MUST Have:

• Experience in PCIe protocol
• Comfort with Makefiles
• Experience with Verifying with other protocols like AXI

al and written communication skills.

NO H1B Transfer at this time.