Senior ASIC Design Verification Engineer – LPU

Anysilicon; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

NVIDIA is seeking an experienced ASIC Verification Engineer in Austin, TX to verify inference accelerators across the ASIC flow. You will work with a team to verify design, architecture, and reference models using SystemVerilog and UVM, building robust verification environments and automated flows.

Requires 8+ years in industry, a Bachelor's in EE/CS/CE, and strong debugging, coverage, and scripting skills (Perl/Python, C/C++). Knowledge of UPF and Verdi/VCS tools is a plus.

Qualifications

• Bachelor’s degree in EE, CS, or CE; 8+ years in industry.
• Experience in ASIC verification and SoC contexts.
• Proficient with SystemVerilog/UVM and verification methodologies.

Responsibilities

• Verify ASIC design and inference accelerators.
• Verify ASIC design, architecture, and reference models.
• Define verification scope and build infrastructure.
• Collaborate with architects, designers, and teams.
• Implement and optimize automated verification flows.
• Stay updated on ASIC verification trends.

Skills

SystemVerilog

UVM

Random stimulus

Functional coverage

Assertions

Debugging

Perl/Python

C/C++

Education

Bachelor's Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience)

Tools

VCS

Verdi

UPF

DFT verification

Job description

NVIDIA, 11001 Lakeline Blvd., Austin, TX 78717

Job Description:

NVIDIA is a leader in computer graphics and AI technology, seeking talented ASIC Verification Engineers to join their dynamic team. This role focuses on verifying the design and implementation of cutting‑edge inference accelerators, contributing to advancements in consumer graphics, self‑driving cars, and AI. NVIDIA offers a supportive and innovative environment where employees can make a significant impact.

Responsibilities:

• Verify the design and implementation of inference accelerators as part of the ASIC Verification team.
• Conduct verification of ASIC design, architecture, reference models, and micro‑architecture using advanced methodologies.
• Define verification scope, develop infrastructure, and ensure design correctness.
• Collaborate with architects, designers, and verification teams throughout the process.
• Implement and optimize automated verification flows to enhance productivity and efficiency.
• Stay updated on trends in ASIC design verification and integrate innovative techniques.

Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).
• 8 years of relevant industry experience.

Skills:

• Experience with building block and SoC level testbench development.
• Strong debugging and analytical skills.
• Proficient in verification using random stimulus, functional coverage, and assertion‑based methodologies.
• Expertise in SystemVerilog and Universal Verification Methodology (UVM).
• Familiarity with design and verification tools such as VCS and Verdi.
• Knowledge of UPF power verification and netlist/DFT verification is a plus.
• Programming experience in Perl/Python and C/C++ is desirable.
• Understanding of ASIC design flow from specification to GDS.
• Knowledge of applying machine learning to ASIC verification processes.