ASIC Physical Design and Timing Engineer - New College Grad 2026

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Job summary

NVIDIA Corporation is seeking a motivated ASIC Timing Engineer to join our team in Santa Clara, CA. This role focuses on driving physical design and timing closure for NVIDIA GPUs, CPUs, DPUs, and SoCs, spanning block to full-chip levels.

The candidate will contribute to frontend/backend flows, including synthesis, floorplanning, timing constraints, and ECO implementations, while collaborating across multiple teams to push cutting-edge AI and accelerator technologies.

Qualifications

• Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
• Proficiency in Timing and Static Timing Analysis (STA).
• Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.
• Expertise with industry standard EDA and timing convergence tools.

Responsibilities

• Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
• Support frontend and backend implementation including synthesis, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Collaborate with cross-functional teams to advance projects and technology.

Skills

Timing analysis

Static Timing Analysis (STA)

Full-chip timing convergence

ECG constraints generation

EDA tools

Programming languages

AI/LLM knowledge

Education

Master's degree in Electrical or Computer Engineering

Tools

Industry standard EDA tools

Job description

## ASIC Physical Design and Timing Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2013177NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.**What you'll be doing:*** Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.* Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.* Play a pivotal role in the success of our innovative projects and advancement of our technology. Work in a cross-functional environment interacting with multiple teams.**What we need to see:*** Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).* Proficiency in Timing and Static Timing Analysis (STA).* Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.* Expertise with industry standard EDA and timing convergence tools.**Ways to stand out from the crowd:*** Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors.* Knowledge of deep sub-micron process nodes.* Proficiency in AI/LLM and programming languages.* Experience in physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus.Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until July 26, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.