ASIC Physical Design and Timing Engineer - New College Grad 2026

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 116,000 - 218,500; Full time

Benefits offered by this job

Comprehensive benefits package

Equity opportunities

Job summary

NVIDIA Gruppe is looking for a talented engineer specialized in Physical Design and Timing Analysis. The successful candidate will be integral in driving the design and optimization of GPUs, CPUs, and SoCs, ensuring technical excellence through collaboration with multiple teams.

A Master’s degree in Electrical or Computer Engineering is required, alongside strong proficiency in Timing Analysis tools. Competitive salaries ranging from 116,000 to 218,500 USD, plus equity and benefits, are offered.

Qualifications

• Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
• Proficiency in Timing and Static Timing Analysis (STA).
• Hands-on experience in full-chip/sub-chip STA and timing convergence.
• Expertise with industry standard EDA and timing convergence tools.

Responsibilities

• Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs.
• Help in driving frontend and backend implementation including synthesis and timing constraints.
• Play a pivotal role in the success of innovative projects and technology advancements.

Skills

Timing and Static Timing Analysis

Hands-on experience in full-chip/sub-chip STA

Expertise with industry standard EDA tools

Proficiency in AI/LLM and programming languages

Education

Master's degree in Electrical or Computer Engineering

Job description

What You'll Be Doing:

• Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Play a pivotal role in the success of our innovative projects and advancement of our technology. Work in a cross-functional environment interacting with multiple teams.

What We Need to See:

• Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
• Proficiency in Timing and Static Timing Analysis (STA).
• Hands‑on experience in full‑chip/sub‑chip STA and timing convergence, timing constraints generation and management.
• Expertise with industry standard EDA and timing convergence tools.

Ways to Stand Out from the Crowd:

• Proven experience in timing convergence for ASICs, CPUs, GPUs or Network processors.
• Knowledge of deep sub‑micron process nodes.
• Proficiency in AI/LLM and programming languages.
• Experience in physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.