ASIC Timing & Physical Design Engineer - Mentoring

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino seeks a skilled SSTA engineer to design and optimize timing flows for ASICs. You will develop timing constraints, run STA, and collaborate with RTL/Arch teams to deliver high-performance, cost-efficient silicon.

The role emphasizes automation, mentoring, and close teamwork within a fast-paced startup-like environment, with a strong focus on delivering reliable timing solutions.

Responsibilities

• Design and optimize timing flows for ASICs in Cupertino.
• Develop timing constraints and run STA to validate silicon timing.
• Collaborate with RTL/Architecture teams to deliver high-performance, cost-efficient silicon.

Job description

Annapurna Labs (U.S.) Inc. in Cupertino seeks a skilled SSTA engineer to design and optimize timing flows for ASICs. You will develop timing constraints, run STA, and collaborate with RTL/Arch teams to deliver high-performance, cost-efficient silicon.

The role emphasizes automation, mentoring, and close teamwork within a fast-paced startup-like environment, with a strong focus on delivering reliable timing solutions.