Static Timing Engineer – ASIC STA Specialist

Annapurna Labs; San Diego (CA); On-site; USD 177,000 - 247,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an experienced STA engineer to design, develop, and optimize block and full-chip static timing analysis flows.

You will write timing constraints, run STA, and provide actionable feedback to cross-functional teams to improve performance and cost. The role requires hands-on scripting (Tcl/Perl/Python) and deep understanding of ASIC physical design from RTL to GDSII, with exposure to sign-off activities.

Qualifications

• Experience scripting or coding.
• BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS.
• Expertise in timing analysis fundamentals.
• 1+ years doing Static Timing Analysis.
• 1+ years with timing constraint development.
• Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others).
• Understanding of ASIC Physical Design from RTL-to-GDSII.
• Understanding of other sign-off activities (ir/em, physical verification, DFT).
• 1+ years of scripting experience with Tcl, Perl or Python.

Responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis.
• Write, debug & validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and give frequent feedback to team members and leads.
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
• Develop scripts to automate running timing analysis and generate reports.
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Skills

Scripting

Timing analysis

Static Timing Analysis

Tcl/Perl/Python scripting

Education

EE/CS degree

Tools

PrimeTime

Tempus

SPICE

SPECTRE

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking an experienced STA engineer to design, develop, and optimize block and full-chip static timing analysis flows.

You will write timing constraints, run STA, and provide actionable feedback to cross-functional teams to improve performance and cost. The role requires hands-on scripting (Tcl/Perl/Python) and deep understanding of ASIC physical design from RTL to GDSII, with exposure to sign-off activities.