Physical Design Engineer - Timing Lead

OHO Group (Lithuania); United States; Remote; USD 140,000 - 210,000; Full time

Benefits offered by this job

Equity participation

Comprehensive benefits

Remote-friendly

Job summary

Startup is seeking a Physical Design Engineer – Timing Lead to own STA, timing convergence, and timing methodology across ASIC/SoC designs. You will lead sign-off, drive timing closure across advanced process technologies, and collaborate with RTL, DFT, and PD teams.

The role emphasizes ownership of timing flows, automation development, and shaping best practices across silicon programs, with competitive compensation, equity, and comprehensive benefits.

Qualifications

• Experience leading STA for ASIC/SoC designs.
• Proven ability to drive timing closure across process techs.
• Strong collaboration with RTL, DFT, and PD teams.
• Experience developing timing methodologies and automation.

Responsibilities

• Lead STA methodology development and sign-off across IP, subsystem, and SoC.
• Drive timing convergence balancing power, performance and area.
• Collaborate with RTL, DFT, and physical design to refine SDC constraints.
• Develop automation to improve STA workflows and efficiency.
• Support timing analysis and sign-off through tapeout.
• Shape timing flows and establish best practices across silicon programs.

Skills

STA

Timing analysis

Digital design

Automation

Education

Bachelor's in Electrical Engineering

Tools

Synopsys PrimeTime

SDC constraints

Job description

Physical Design Engineer – Timing Lead | Startup | Remote

A growing startup building custom accelerators is looking for a Physical Design Engineer – Timing Lead to take ownership of static timing analysis (STA), timing convergence, and methodology development across advanced ASIC and SoC designs.

This is a high-impact position offering significant technical ownership, with the opportunity to develop and improve timing methodologies, influence implementation decisions, and work closely with cross-functional engineering teams throughout the silicon development lifecycle.

Key Responsibilities

• Lead STA methodology development, timing closure, and sign-off across IP, subsystem, and SoC designs.
• Drive timing convergence across advanced process technologies, balancing power, performance, and area (PPA).
• Collaborate with RTL, DFT, and physical design teams to develop and refine SDC constraints.
• Develop automation and scripting solutions to improve STA workflows and efficiency.
• Support timing analysis and sign-off activities throughout the design and tapeout process.
• Experience collaborating across RTL, DFT, and physical implementation teams.

This is a strategically important hire offering significant ownership over STA and timing methodology within the engineering organization.

The successful candidate will have the autonomy to shape timing flows, drive technical decisions, and establish best practices across complex silicon development programs.

The position offers competitive compensation, equity participation, comprehensive benefits, and opportunities for long-term technical growth.