ASIC Physical Design Engineer - Timing & STA Specialist

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a skilled STA engineer to design and optimize timing analysis flows for block and full-chip level silicon. You will write constraints, run analysis, and collaborate with RTL/Arch teams to deliver reliable performance.

Responsibilities include scripting, tool automation, and mentoring teammates while adhering to high standards for cost and quality in a fast-paced environment.

Qualifications

• Experience scripting or coding.
• Strong timing analysis fundamentals.
• 1+ years in Static Timing Analysis.
• 1+ years with timing constraint development.
• Experience with EDA tools such as PrimeTime or Tempus.

Responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis.
• Write, debug & validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and provide feedback to the team.
• Guide on fixing timing issues and generating ECOs.
• Develop scripts to automate timing analysis and reports.

Skills

Scripting

Timing analysis

EDA tools

RTL-to-GDSII

Python/Tcl/Perl

Education

BS + 6yrs in EE/CS

MS + 4yrs in EE/CS

PhD + 2yrs in EE/CS

Tools

PrimeTime

Tempus

ECO tools

Parasitic extraction tools

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a skilled STA engineer to design and optimize timing analysis flows for block and full-chip level silicon. You will write constraints, run analysis, and collaborate with RTL/Arch teams to deliver reliable performance.

Responsibilities include scripting, tool automation, and mentoring teammates while adhering to high standards for cost and quality in a fast-paced environment.