ASIC Timing & Physical Design Engineer

Amazon Web Services (AWS); Cupertino (CA); Vor Ort; USD 157.000 - 213.000; Vollzeit

Benefits dieser Stelle

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Zusammenfassung

Amazon Energy? Annapurna Labs (U.S.) Inc. is seeking a skilled SSTA engineer to design and optimize timing flows for ASICs in Cupertino. You will develop timing constraints, run STA, and collaborate with RTL/Arch teams to deliver high-performance, cost-efficient silicon.

The role emphasizes automation, mentoring, and close teamwork within a fast-paced startup-like environment, with a strong focus on delivering reliable, scalable timing solutions.

Qualifikationen

• Experience scripting or coding.
• BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS.
• Expertise in timing analysis fundamentals.
• 1+ years doing Static Timing Analysis.
• 1+ years with timing constraint development.
• Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others).
• Understanding of ASIC Physical Design from RTL-to‑GDSII.
• Understanding of other sign‑off activities (ir/em, physical verification, DFT).
• 1+ years of scripting experience with Tcl, Perl or Python.

Aufgaben

• Develop & maintain flows for block and full‑chip level static timing analysis.
• Write, debug & validate timing constraints for blocks and full‑chip.
• Run Static Timing Analysis and give frequent feedback to team members and leads.
• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
• Develop scripts to automate running timing analysis and generate reports.
• Be a highly‑valued member of our start‑up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Kenntnisse

Scripting experience

Static Timing Analysis

Timing constraints development

EDA tools experience

RTL-to-GDSII understanding

Ausbildung

BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS

Tools

PrimeTime

Tempus

SPICE / SPECTRE

Jobbeschreibung

Amazon Energy? Annapurna Labs (U.S.) Inc. is seeking a skilled SSTA engineer to design and optimize timing flows for ASICs in Cupertino. You will develop timing constraints, run STA, and collaborate with RTL/Arch teams to deliver high-performance, cost-efficient silicon.

The role emphasizes automation, mentoring, and close teamwork within a fast-paced startup-like environment, with a strong focus on delivering reliable, scalable timing solutions.