Physical Design Engineer - Timing Lead

Oho Group; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Austin-based startup building custom accelerators is seeking a Physical Design Engineer – Timing Lead to own static timing analysis, timing convergence, and timing methodology across advanced ASIC/SoC designs.

You will influence implementation decisions, develop timing flows, and work with RTL, DFT, and physical teams to ensure robust sign-off and successful tapeouts, with competitive compensation and equity opportunities.

Qualifications

• Proven experience leading static timing analysis and timing closure.
• Ability to develop and refine timing methodologies across complex designs.
• Collaborates with RTL, DFT, and physical design teams to optimize STA workflows.

Responsibilities

• Lead STA methodology development, timing closure, and sign-off across IP, subsystem, and SoC designs.
• Drive timing convergence across advanced process technologies, balancing power, performance, and area (PPA).
• Collaborate with RTL, DFT, and physical design teams to develop and refine SDC constraints.
• Develop automation and scripting solutions to improve STA workflows and efficiency.
• Support timing analysis and sign-off activities throughout the design and tapeout process.
• Experience collaborating across RTL, DFT, and physical implementation teams.

Skills

STA leadership

Timing analysis

SDC constraints

Automation scripting

Job description

Physical Design Engineer – Timing Lead | Startup | Austin

A growing startup building custom accelerators is looking for a Physical Design Engineer – Timing Lead to take ownership of static timing analysis (STA), timing convergence, and methodology development across advanced ASIC and SoC designs.

This is a high-impact position offering significant technical ownership, with the opportunity to develop and improve timing methodologies, influence implementation decisions, and work closely with cross-functional engineering teams throughout the silicon development lifecycle.

Key Responsibilities

• Lead STA methodology development, timing closure, and sign-off across IP, subsystem, and SoC designs.
• Drive timing convergence across advanced process technologies, balancing power, performance, and area (PPA).
• Collaborate with RTL, DFT, and physical design teams to develop and refine SDC constraints.
• Develop automation and scripting solutions to improve STA workflows and efficiency.
• Support timing analysis and sign-off activities throughout the design and tapeout process.
• Experience collaborating across RTL, DFT, and physical implementation teams.

This is a strategically important hire offering significant ownership over STA and timing methodology within the engineering organization.

The successful candidate will have the autonomy to shape timing flows, drive technical decisions, and establish best practices across complex silicon development programs.

The position offers competitive compensation, equity participation, comprehensive benefits, and opportunities for long-term technical growth.