ASIC Technical Program Manager: Tape-Out Lead

The Consensus; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, and vision

Housing subsidy for commuting

Relocation support to San Jose

Wellness benefits

Daily lunch and dinner in office

Unlimited compute budget

Job summary

Etched is seeking a highly skilled ASIC Technical Program Manager to join our silicon team. This hands-on role drives execution across the RTL-to-GDSII flow and oversees coordination between Physical Design, DFT, DV, and RTL, while managing external vendors and IP providers.

You will shepherd tape-out milestones and ECO cycles with urgency befitting a first-silicon program. The ideal candidate has real tape-out experience, strong cross-team collaboration skills, and the ability to communicate

Qualifications

• At least one full ASIC tape-out experience end-to-end.
• Solid understanding of RTL-to-GDSII flow and inter-team handoffs.
• 5+ years in technical/hardware program management or similar role.
• Experience with external EDA vendors or implementation partners.
• Excellent follow-through and proactive dependency management.

Responsibilities

• Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams.
• Engage external vendors and hold them to timelines and deliverables.
• Identify risks, schedule slippage, and develop mitigation strategies.
• Plan and execute complex multi-team hardware programs and tape-outs.
• Provide regular updates to engineering leads and executives.
• Coordinate tooling and dashboards to improve engineering visibility.

Skills

ASIC tape-out

RTL-to-GDSII flow

Vendor management

Cross-functional coordination

Communication skills

Education

Bachelor's degree in Engineering, Computer Science, or related field

Tools

EDA tools

IP/implementation partners

Job description

Etched is seeking a highly skilled ASIC Technical Program Manager to join our silicon team. This hands-on role drives execution across the RTL-to-GDSII flow and oversees coordination between Physical Design, DFT, DV, and RTL, while managing external vendors and IP providers.

You will shepherd tape-out milestones and ECO cycles with urgency befitting a first-silicon program. The ideal candidate has real tape-out experience, strong cross-team collaboration skills, and the ability to communicate