Remote Signal & Power Integrity Leader for ASIC Packaging

Cisco Systems; Reno (NV); Hybrid; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

401(k) with Cisco matching

Paid parental leave

Disability coverage

Stock units (RSUs)

Job summary

Cisco Silicon One in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to head SI/PI efforts for next-gen ASIC packaging. You will define design rules, analyze SI/PI, and drive post-layout extraction across interposer, substrate, and PCB for Cisco platforms.

The role requires leadership of a multi-disciplined team, expertise in 56G PAM4/SerDes, and collaboration with system partners to resolve complex technical issues using advanced design rules.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of signal or power integrity experience, or a Master's with 8+ years, or a PhD with 5+ years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with scattering and impedance network parameters.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead the Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging.
• Develop, document, and implement design rules for ultra-high-speed signaling ensuring power, performance, and area goals.
• Analyze substrate SI/PI and collaborate with layout for optimal interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume, high-quality releases including post-layout extraction and reporting.
• Mentor and support the SI team and influence packaging/hardware teams.

Job description

Cisco Silicon One in San Jose, CA is seeking a Signal and Power Integrity Technical Leader to head SI/PI efforts for next-gen ASIC packaging. You will define design rules, analyze SI/PI, and drive post-layout extraction across interposer, substrate, and PCB for Cisco platforms.

The role requires leadership of a multi-disciplined team, expertise in 56G PAM4/SerDes, and collaboration with system partners to resolve complex technical issues using advanced design rules.