ASIC Interconnect & Fabric Design Engineer

AGL Technologies Inc.; City of Utica (NY); On-site; USD 180,000 - 240,000; Full time

Job summary

AGL Technologies Inc. is seeking a lead architect to redesign our primary system fabric and memory interconnect in a critical architecture role.

You will collaborate with technical leadership and the core logic team to re-architect the interconnect hierarchy for modular, plug-and-play integration between custom processor cores, high-bandwidth memory interfaces, and system peripherals. You will drive RTL implementation, protocol conversion, and verification to ensure high performance, scalable

Qualifications

• 5+ years of ASIC RTL design experience for SoC fabric and interconnects.
• Deep knowledge of AMBA, TileLink, or related bus protocols.
• Strong background in CDC design and asynchronous techniques.

Responsibilities

• Lead interconnect architecture and define requirements and micro-architecture.
• Design modular bus interfaces, bridges, and adapters for IP integration.
• Write RTL for crossbars, bus bridges, and protocol converters.
• Develop verification environments, assertions, and testbenches.
• Tune performance, latency, and arbitration to avoid memory bottlenecks.

Skills

ASIC RTL design

SoC interconnect

CDC design

Education

B.S. Electrical Engineering

Tools

AMBA AXI4

TileLink

CDC tools

Job description

In this critical architecture and implementation role, you will lead the redesign of our primary system fabric and memory interconnect. You will collaborate directly with technical leadership and the core logic team to re-architect our interconnect hierarchy, enabling modular, plug-and-play integration between custom processor cores, high-bandwidth memory/DDR interfaces, and system peripherals.

Key responsibilities

• Interconnect architecture: Collaborate with system leads to define requirements, protocol standards, and micro-architecture for a modular, high-performance system interconnect (AXI, TileLink, or custom fabric).
• Plug-and-play framework: Design modular bus interfaces, bridge blocks, and adapter logic to streamline future IP block integration and scalability.
• RTL implementation: Write clean, high-performance RTL for crossbars, bus bridges, clock-domain crossing (CDC) async FIFOs, and protocol converters.
• Protocol & interconnect verification: Develop testbenches, assertions, and constrained-random verification environments to validate protocol compliance, corner cases, and deadlock avoidance.
• Performance tuning: Optimize fabric latency, throughput, arbitration policies, and bus widths to prevent memory bottlenecks for the custom processor pipeline.

Required qualifications

• Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
• Experience: 5+ years of experience in ASIC RTL design focused on SoC fabric, system interconnects, and bus protocols.
• Bus protocol expertise: Deep, hands-on knowledge of AMBA standards (AXI4, AHB, APB, CHI/ACE) or open standards like TileLink/OCP.
• CDC & asynchronous design: Mastery of clock-domain crossings, synchronizers, asynchronous FIFOs, and CDC verification tools.
• Processor interface experience: Proven experience interfacing memory buses directly to RISC-V, ARM, or proprietary custom processor pipelines.
• RTL & verification skills: Advanced RTL skills for protocol checking and verification.