ASIC Peripheral & SoC Integration Engineer

AGL Technologies Inc.; City of Utica (NY); On-site; USD 120,000 - 180,000; Full time

Job summary

AGL Technologies Inc. in Utica, NY is seeking an experienced RTL designer to bridge silicon design and low-level software across a 12nm SoC.

You will own the complete lifecycle from RTL to verification, register map creation, and driver development for I2C, SPI, MDIO, UART, and GPIO. Collaborating with software teams, you will bring up peripherals, configure buses, and support FPGA emulation and post-silicon validation.

Qualifications

• 3–6 years of experience in ASIC RTL design and embedded software integration.
• Proficiency in RTL for synthesizable design and verification.
• Deep understanding of standard serial and management protocols (SPI, I2C, MDIO/MDC, UART).

Responsibilities

• Bridge silicon design and low-level software, owning RTL, verification, and driver development.
• Create register maps and bring-up low-level drivers for hardware testing and software handoff.
• Integrate peripherals to on-chip buses and configure interrupt routing to the system controller.
• Build block testbenches to validate protocols and bus behavior across the SoC.
• Support silicon bring-up, FPGA emulation, and post-silicon validation.

Skills

RTL design

Embedded software

C programming

Bus architectures

Register-level development

Tools

SystemVerilog

VHDL

UVM

C/C++

Job description

In this role, you will bridge the gap between silicon design and low-level software. You will own the complete lifecycle (RTL design, verification, register map creation, and driver development) for standard management and peripheral interfaces (I2C, SPI, MDIO, UART, GPIO) across our 12nm SoC architecture.

Key responsibilities

• Peripheral RTL design: Implement, configure, and integrate low-speed peripheral and control IPs (I2C, SPI, MDIO, etc.) into the main SoC interconnect.
• Block verification: Build block-level testbenches (SystemVerilog/VHDL/UVM or C/Assembly-based verification) to validate protocols, register behavior, and bus attachments.
• Driver development: Write clean, low-level drivers and bring-up code for hardware testing and software team handoff.
• SoC bus integration: Connect peripherals to on-chip buses and configure interrupt routing to the system controller/PLIC.
• Silicon bring-up support: Assist with FPGA emulation and post-silicon laboratory bring-up for control interface validation.

Required qualifications

• Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
• Experience: 3–6 years of experience in ASIC RTL design and embedded software integration.
• RTL & hardware: Solid proficiency in RTL for synthesizable design and verification.
• Interface standards: Deep understanding of standard serial and management protocols (SPI, I2C, MDIO/MDC, UART).
• Low-level C programming: Hands-on experience writing bare-metal drivers, register-level bit manipulation, and low-level hardware abstraction layers.
• Bus architectures: Familiarity with standard bus protocols (APB, AHB, AXI, TileLink) and register generation tools. Ability to interface to custom system fabric.