Hardware Design Engineer

Rambus.com; Hillsboro (OR); Sur place; USD 100 000 - 130 000; Plein temps

Résumé du poste

Rambus is seeking a qualified candidate for a role in Hillsboro, Oregon, emphasizing strong expertise in System Verilog/Verilog RTL design. Responsibilities include RTL coding, integration, and customer support. The ideal candidate will have substantial experience in ASIC or FPGA design, strong communication skills, and a Bachelor's in Electrical Engineering (BSEE). Expertise in simulation tools and ability to work independently are preferred. Join our innovative team to contribute to cutting-edge memory solutions.

Qualifications

• 5+ years of logic design experience is required.
• Strong communication and project management skills are essential.
• Willingness to learn quickly and work independently.

Responsabilités

• Design architecting and trade-off analysis.
• Perform RTL coding and verification.
• Integrate and verify Memory Controller + PHY.

Connaissances

System Verilog/Verilog RTL design expertise

Questa/Incisive/VCS simulator experience

Python/Perl/Tcl scripting experience

ASIC/FPGA design experience

Solid communication skills

Project management skills

Logic design experience

Formation

BSEE

Description du poste

Responsibilities

• Design architecting and trade-off analysis
• RTL coding and verification
• Memory Controller + PHY integration and verification
• Customer delivery and support

Qualifications

Strong System Verilog/Verilog RTL design expertise

• Questa/Incisive/VCS simulator experience
• Python/Perl/Tcl scripting experience
• Significant ASIC and/or FPGA design experience
• Ability to learn quickly and work independently
• Solid communication and project management skills
• 5+ years of logic design experience
• BSEE

Definite Plus:

• ASIC synthesis, timing constraint, CDC/RDC experience
• Verification experience
• Memory (HBM, GDDR, LPDDR, DDR) expertise
• AMBA AXI or CHI design experience
• Located in the Hillsboro, Oregon area

Training:

• Provided as needed