ASIC Engineer, Implementation

Anysilicon; Austin (TX); Sur place; USD 170 000 - 240 000; Plein temps

Résumé du poste

Meta's Silicon Engineering organization is seeking a Staff ASIC Implementation Engineer in Austin to lead the physical implementation and synthesis of complex custom ASICs for AI and data center applications.

You will own end-to-end flows, drive timing closure, and develop automation to improve quality. You will mentor engineers and help shape silicon strategy.

Candidates should have 8+ years of ASIC implementation experience and hands-on with major EDA tools.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8 years of experience in ASIC implementation, including logic synthesis and timing closure for complex designs.
• Experience with EDA tools like Synopsys Design Compiler or Cadence Genus.
• Experience managing synthesis constraints and driving timing closure across multi-million gate designs.

Responsabilités

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, and design-for-test integration.
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints.
• Drive timing closure strategies across hierarchical design partitions, collaborating with RTL and physical design engineers.
• Develop and maintain synthesis scripts and automation infrastructure to enhance implementation quality.
• Generate SOC floorplans at various levels and support block implementation owners in synthesis and physical design.
• Perform top-level logical and physical connectivity analysis for timing and area optimization.
• Partner with architecture and RTL teams to provide feedback on design decisions affecting area, power, and timing.
• Define and enforce design rules and quality sign-off criteria for tape-out readiness.
• Identify and resolve cross-functional implementation risks, communicating status to stakeholders.
• Mentor engineers on implementation methodology and timing analysis techniques.
• Contribute to long-term silicon implementation strategy and evaluate new EDA tools.

Connaissances

ASIC implementation

Synthesis methods

Static timing analysis

Automation scripting

Cross-functional collaboration

Problem solving

Formation

Bachelor's degree in Computer Science/Engineering or related

Outils

Synopsys Design Compiler

Cadence Genus

Description du poste

Meta's Silicon Engineering organization is seeking a Staff ASIC Implementation Engineer to lead the physical implementation and synthesis of complex custom ASICs. This role involves driving the architectural and methodological decisions that shape Meta's silicon roadmap, ensuring high-performance and power-efficient silicon solutions for AI and data center applications.

Responsibilities:

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, and design-for-test integration.
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints.
• Drive timing closure strategies across hierarchical design partitions, collaborating with RTL and physical design engineers.
• Develop and maintain synthesis scripts and automation infrastructure to enhance implementation quality.
• Generate SOC floorplans at various levels and support block implementation owners in synthesis and physical design.
• Perform top-level logical and physical connectivity analysis for timing and area optimization.
• Partner with architecture and RTL teams to provide feedback on design decisions affecting area, power, and timing.
• Define and enforce design rules and quality sign-off criteria for tape-out readiness.
• Identify and resolve cross-functional implementation risks, communicating status to stakeholders.
• Mentor engineers on implementation methodology and timing analysis techniques.
• Contribute to long-term silicon implementation strategy and evaluate new EDA tools.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8 years of experience in ASIC implementation, including logic synthesis and timing closure for complex designs.
• Experience with EDA tools like Synopsys Design Compiler or Cadence Genus.
• Experience managing synthesis constraints and driving timing closure across multi-million gate designs.

Skills:

• Expertise in ASIC implementation and synthesis methodologies.
• Strong knowledge of static timing analysis and design-for-test integration.
• Proficiency in scripting languages for automation.
• Ability to collaborate effectively with cross-functional teams.
• Strong problem-solving skills and attention to detail.