ASIC Implementation Engineer, Static Verification

Meta; Sunnyvale (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Meta in Sunnyvale, CA seeks an ASIC Frontend Implementation Engineer specializing in RTL to netlist flow for data center SoCs. You will collaborate with design, DV, and emulation teams to deliver optimized gate-level netlists capable of meeting timing, area and power targets.

Responsibilities include RTL lint, CDC/RDC analysis, DFT coverage improvements, and automation scripting to streamline frontend tooling.

Qualifications

• BS in computer science, computer engineering or a related field, or equivalent practical experience.
• Experience with front-end implementation from RTL to netlist, including timing and optimization.

Responsibilities

• Perform flat and hierarchical CDC and reset domain crossing analyses and sign-off.
• Conduct RTL linting, DFT analysis, and improve coverage for stuck-at faults.
• Run logic/physical synthesis and generate optimized gate-level netlists.
• Develop automation scripts and methodologies for FE-tools.

Skills

RTL to netlist

RTL Lint

CDC analysis

Timing constraints

Synthesis

DFT analysis

Automation scripts

Education

Bachelor's degree in CS/CE or related

Tools

Lint

CDC tools

RDC

DFT tools

Synthesis tools

Job description

# ASIC Implementation Engineer, Static VerificationSunnyvale, CA Design+ 5 moreApply nowMeta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.---## ASIC Implementation Engineer, Static Verification Responsibilities* Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC* Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC* Perform RTL Lint and work with the Designers to create waivers* Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults* Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power* Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)* Work closely with the Design Engineers, DV Engineers, and Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback## Minimum Qualifications* Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience