ASIC Floorplan Engineer - Early-Career with Equity

NVIDIA AI; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Floorplan Design Engineer at New College Graduate level to design and optimize floorplans for cutting-edge GPUs and SoCs. You will partner with architects, design leads, and physical design teams to influence early chip layout and timing closure.

Candidates should have a strong hardware background (VLSI/Computer Architecture) and hands-on Verilog/SystemVerilog, CAD tooling, and scripting (Python/Perl/C/C++).

Qualifications

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• Deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Experience in Verilog, System Verilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience

Responsibilities

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Skills

Python

Perl

C/C++

Verilog

SystemVerilog

CAD tools

Chip floorplan

Timing closure

Strong communication

Education

Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

CAD tools

Job description

NVIDIA is seeking an ASIC Floorplan Design Engineer at New College Graduate level to design and optimize floorplans for cutting-edge GPUs and SoCs. You will partner with architects, design leads, and physical design teams to influence early chip layout and timing closure.

Candidates should have a strong hardware background (VLSI/Computer Architecture) and hands-on Verilog/SystemVerilog, CAD tooling, and scripting (Python/Perl/C/C++).