Senior ASIC Floorplan Design Engineer

NVIDIA; Santa Clara (CA); On-site; USD 196,000 - 310,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is looking for a Senior ASIC Floorplan Design Engineer in Santa Clara, California. This role involves designing and optimizing floorplans for cutting-edge GPUs and SoCs, requiring extensive hardware engineering expertise. You will collaborate with different teams to solve design issues and optimize chip execution efficiency.

Ideal candidates will have a Master's degree in Electrical Engineering or related fields with over 12 years of experience in hardware engineering, particularly in VLSI. The compensation package includes competitive salary and equity options.

Qualifications

• 12+ years of relevant work experience.
• Deep hardware engineering background with concentration in VLSI and/or Computer Architecture.
• Experience with CAD and physical design methodologies, chip floorplan, power/clock distribution, packaging, P&R, and timing closure.

Responsibilities

• Develop and optimize floorplans during early chip development.
• Drive area review process and collaborate with ASIC design team.
• Solve timing and routing congestion issues with design teams.
• Build tools and improve existing infrastructure for chip optimization.

Skills

VLSI

Computer Architecture

Verilog

System Verilog

Python

Perl

C/C++ programming

Interpersonal skills

Education

Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

CAD tools

Job description

Senior ASIC Floorplan Design Engineer

NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology‑focused company impacting product lines ranging from consumer graphics to self‑driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you will be doing:

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

What we need to see:

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
• 12+ years of relevant work experience
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Experience in Verilog, System Verilog or similar HVL
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience

Ways to stand out from the crowd:

• Experience in driving development of large scale ASIC floorplan is a huge plus.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD for Level 5, and 232,000 USD - 368,000 USD for Level 6.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 25, 2026.

This posting is for an existing vacancy.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.