ASIC Floorplan Engineer - New Grad 2026 | Equity & Impact

Nvidia Corporation in; Santa Clara (CA); On-site; USD 120,000 - 210,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a ASIC Floorplan Design Engineer for a new college graduate. You will design and optimize floorplans for leading SoCs and GPUs, collaborating with architects, design leads, and package leads to influence early chip development.

This role requires a MS in EE/CS/CE, a strong background in VLSI/Computer Architecture, Verilog/SystemVerilog, CAD and physical design experience, and programming in Python, Perl, and C/C++.

Qualifications

• Master's degree required in EE/CS/CE or equivalent.

Responsibilities

• Develop and optimize floorplans with architects and design leads.
• Drive area review process and identify improvements in area, interconnect and floorplan.
• Solve timing and routing congestion with timing closure and design decisions.
• Build tools and improve infrastructure to optimize chip area and speed.

Skills

Verilog/SystemVerilog

C/C++

Python

Perl

Floorplanning

CAD/Physical design tools

Education

Masters in Electrical Engineering, Computer Science, or Computer Engineering

Tools

CAD tools

Job description

NVIDIA is seeking a ASIC Floorplan Design Engineer for a new college graduate. You will design and optimize floorplans for leading SoCs and GPUs, collaborating with architects, design leads, and package leads to influence early chip development.

This role requires a MS in EE/CS/CE, a strong background in VLSI/Computer Architecture, Verilog/SystemVerilog, CAD and physical design experience, and programming in Python, Perl, and C/C++.