ASIC Design Engineer, Tools & Methodology (Hybrid, Equity)

Nvidia Corporation in; Austin (TX); Hybrid; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an ASIC Design Engineer with proven hardware design and methodology expertise to join our world-class team to help amplify human creativity and intelligence.

Based in Austin, TX, you will develop and deploy in-house tools and workflows, own tools that verify common design blocks, and act as a DevOps engineer for automated RTL generation, integrating new workflows into IP development environments.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of proven experience preferred.
• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
• Proficiency in scripting using modern Python and/or Perl.
• Experience with Unix/Linux shell scripting and Makefiles.
• Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Responsibilities

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
• Take ownership of tools that verify common design blocks used in all products at NVIDIA.
• Act as a DevOps engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
• Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Skills

Verilog experience

Python scripting

Unix/Linux shell

Team collaboration

Communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Job description

NVIDIA is seeking an ASIC Design Engineer with proven hardware design and methodology expertise to join our world-class team to help amplify human creativity and intelligence.

Based in Austin, TX, you will develop and deploy in-house tools and workflows, own tools that verify common design blocks, and act as a DevOps engineer for automated RTL generation, integrating new workflows into IP development environments.