ASIC Floorplan Engineer - New Grad Impact on SoCs

NVIDIA; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in California is seeking a new college graduate for an ASIC Floorplan Design Engineer role to contribute to the design of leading SoCs and GPUs. You will collaborate with architects, design leads, and physical design teams to craft floorplans, optimize chip area, and address power and timing considerations early in chip development.

Candidates should hold a Master’s in Electrical Engineering, Computer Science, or Computer Engineering, with a strong hardware background in VLSI/architecture

Qualifications

• Master’s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Experience in Verilog, SystemVerilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
• Python, Perl and C/C++ programming language experience

Responsibilities

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Skills

VLSI knowledge

Hardware engineering

Python

C/C++

Verilog/SystemVerilog

Communication

Education

Master's degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

CAD tools

Physical design flow

P&R

Job description

NVIDIA in California is seeking a new college graduate for an ASIC Floorplan Design Engineer role to contribute to the design of leading SoCs and GPUs. You will collaborate with architects, design leads, and physical design teams to craft floorplans, optimize chip area, and address power and timing considerations early in chip development.

Candidates should hold a Master’s in Electrical Engineering, Computer Science, or Computer Engineering, with a strong hardware background in VLSI/architecture