ASIC Engineering Technical Leader

Anysilicon; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Cisco’s Common Hardware Group is seeking a senior ASIC Design Engineer to design and implement advanced ASICs powering networking hardware. You will participate in architecture discussions, write specifications, and deliver RTL that meets stringent timing and performance targets.

The role requires mentoring junior engineers, collaborating with verification and physical design teams, and performing post-silicon validation in the lab. A strong track record from spec to tape-out is essential.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• Advanced degree preferred for senior roles.
• Proven track record in ASIC design from spec to tape-out.

Responsibilities

• Participate in chip architecture definition and discussions.
• Author design specifications and engage in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Define, evolve, and support design methodology.
• Mentor junior engineers in project tasks and problem-solving.
• Collaborate with the verification team to address design bugs and ensure code coverage.
• Work closely with the physical design team to resolve timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Conduct diagnostic and post-silicon validation tests in the lab.

Skills

Verilog RTL

ASIC Design

Timing Analysis

RTL Debugging

Debugging

Architecture development

Communication skills

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Python scripting

Perl scripting

TCL scripting

Shell scripting

Job description

Join Cisco's Common Hardware Group (CHG) as a key contributor in designing and developing advanced ASICs for networking hardware that powers Cisco’s core Switching, Routing, and Wireless products. This role offers the opportunity to work on cutting-edge technology that impacts enterprises, service providers, and nonprofit organizations globally.

Responsibilities:

• Participate in chip architecture definition and discussions.
• Author design specifications and engage in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Define, evolve, and support design methodology.
• Mentor junior engineers in project tasks and problem-solving.
• Collaborate with the verification team to address design bugs and ensure code coverage.
• Work closely with the physical design team to resolve timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Conduct diagnostic and post-silicon validation tests in the lab.

Qualifications:

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC Design experience, or a Master’s degree with 6+ years, or a PhD with 3 years in ASIC Design.
• Experience in interactive and waveform debugging.
• Proven track record of delivering ASIC designs from specification to tape-out.
• Experience in architecture and micro-architecture development.

Skills:

• Experience resolving setup and hold timing violations with RTL modification.
• Scripting skills in Python, Perl, TCL, or shell programming.
• Strong troubleshooting and debugging abilities.
• Excellent written and verbal communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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