Senior ASIC Architect & Technical Leader

Anysilicon; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Cisco’s Common Hardware Group is seeking a senior ASIC Design Engineer to design and implement advanced ASICs powering networking hardware. You will participate in architecture discussions, write specifications, and deliver RTL that meets stringent timing and performance targets.

The role requires mentoring junior engineers, collaborating with verification and physical design teams, and performing post-silicon validation in the lab. A strong track record from spec to tape-out is essential.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field.
• Advanced degree preferred for senior roles.
• Proven track record in ASIC design from spec to tape-out.

Responsibilities

• Participate in chip architecture definition and discussions.
• Author design specifications and engage in micro-architecture specification reviews.
• Implement Verilog RTL to meet timing and performance requirements.
• Define, evolve, and support design methodology.
• Mentor junior engineers in project tasks and problem-solving.
• Collaborate with the verification team to address design bugs and ensure code coverage.
• Work closely with the physical design team to resolve timing and place-and-route issues.
• Triage, debug, and root cause simulation, software bring-up, and customer failures.
• Conduct diagnostic and post-silicon validation tests in the lab.

Skills

Verilog RTL

ASIC Design

Timing Analysis

RTL Debugging

Debugging

Architecture development

Communication skills

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Python scripting

Perl scripting

TCL scripting

Shell scripting

Job description

Cisco’s Common Hardware Group is seeking a senior ASIC Design Engineer to design and implement advanced ASICs powering networking hardware. You will participate in architecture discussions, write specifications, and deliver RTL that meets stringent timing and performance targets.

The role requires mentoring junior engineers, collaborating with verification and physical design teams, and performing post-silicon validation in the lab. A strong track record from spec to tape-out is essential.