ASIC Engineer, Physical Design

Meta; Austin, Sunnyvale (TX, CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an experienced engineer to lead the physical design of complex ASIC blocks, overseeing the entire implementation flow. You will define methodologies and optimize designs to meet power, performance, and area targets.

The ideal candidate has over eight years of ASIC physical design experience, proficiency with key industry-standard EDA tools, and a strong background in cross-functional collaboration. Compensation ranges from $178,000 to $250,000, plus bonuses and equity.

Qualifications

• 8+ years of experience in ASIC physical design, from floorplanning to tapeout.
• Experience with static timing analysis and multi-corner multi-mode closure.
• Familiarity with low-power design techniques.

Responsibilities

• Lead physical implementation of complex ASIC blocks.
• Define and drive physical design methodology and best practices.
• Perform timing analysis and ensure timing closure.

Skills

ASIC physical design

EDA tools knowledge (Synopsys, Cadence)

Static timing analysis

Cross-functional collaboration

Scripting (Python, Tcl)

Education

Bachelor's degree in Computer Science or related field

Tools

Synopsys IC Compiler

Cadence Innovus

Primetime

Calibre

Job description

Summary

Meta is building custom silicon to power the next generation of infrastructure and consumer hardware, including data center accelerators and wearable devices. The Physical Design team is responsible for translating RTL into manufacturable, high-performance silicon by owning the full physical implementation flow from floorplanning through signoff. In this role, you will drive physical design strategy for complex ASIC blocks, define implementation methodologies, and partner closely with architecture, design, and verification teams to deliver chips that meet aggressive power, performance, and area targets at advanced process nodes.

Responsibilities

1. Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodes
2. Define and drive physical design methodology, flow development, and best practices across the physical design organization
3. Perform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoff
4. Drive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniques
5. Collaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design‑for‑manufacturability
6. Partner with custom layout and circuit design teams to integrate analog and mixed‑signal blocks into the digital physical implementation flow
7. Develop and maintain physical design scripts, automation flows, and runsets to improve team productivity and implementation quality
8. Conduct design rule check and layout versus schematic verification, resolving violations in coordination with foundry and design teams
9. Evaluate and qualify new EDA tools and process design kits, providing technical recommendations to improve physical implementation outcomes
10. Mentor other engineers on physical design techniques, flow improvements, and signoff methodology across the team

Minimum Qualifications

1. Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
2. 8+ years of experience in ASIC physical design, including hands‑on ownership of full physical implementation flows from floorplanning through tapeout
3. 8+ years of experience with industry-standard EDA tools for placement, routing, clock tree synthesis, and signoff (e.g., Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre)
4. Experience with static timing analysis, timing constraint development, and multi-corner multi-mode closure at advanced process nodes (7nm or below)
5. Experience defining and improving physical design methodologies, flows, and automation scripts at an organizational level
6. Experience collaborating cross‑functionally with RTL design, circuit design, and verification teams to resolve physical implementation challenges

Preferred Qualifications

1. Familiarity with low‑power design techniques including power gating, multi‑voltage domain implementation, and dynamic voltage and frequency scaling
2. Proficiency in scripting languages such as Python or Tcl for EDA flow automation and physical design data analysis
3. Experience with 3D‑IC, chiplet integration, or advanced packaging physical design considerations
4. Experience with physical implementation of machine learning accelerators, network‑on‑chip architectures, or high‑bandwidth memory interfaces

Public Compensation

$178,000/year to $250,000/year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program in certain locations, as required by law.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].