Senior SOC Emulation Engineer — IP Bring-Up Expert

Amazon; Sunnyvale (CA); On-site; USD 183,000 - 248,000; Full time

Job summary

Amazon is seeking an experienced Sr. SOC Emulation Engineer in Sunnyvale to define emulation bring-up environments for ASIC and system-level emulation.

You will work with RTL, verification, and silicon teams to validate designs on emulation platforms and develop C++-based testbenches for robust verification. The role requires deep expertise in Verilog/SystemVerilog, C/C++, and scripting, plus a track record in emulation bring-up and debugging.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering.
• 10+ years of experience in SOC emulation and validation.
• Strong expertise with industry-standard emulation platforms (e.g., Synopsys Zebu, Cadence Palladium, Mentor Veloce).
• Proficiency in Verilog/SystemVerilog/VHDL.
• Experience with C/C++ and scripting (Python, Tcl, Perl).
• Strong debugging and problem-solving skills.

Responsibilities

• Build and bring-up emulation models for complex SOC designs.
• Develop and maintain emulation environments and methodologies.
• Debug complex hardware issues using emulation platforms.
• Develop and maintain C++ based emulation testbench framework.
• Create and execute verification test plans.
• Interface with RTL, verification and silicon validation engineers to validate designs on emulation platforms.
• Enable and partner with software team on software bring-up and root-cause bugs.
• Optimize emulation performance and resource utilization.
• Document processes, methodologies, and technical specifications.

Skills

C++

Python

SystemVerilog

Debugging

Education

Bachelor's degree in CS/CE/EE

Master's preferred

Tools

Synopsys Zebu

Cadence Palladium

Mentor Veloce

Job description

Amazon is seeking an experienced Sr. SOC Emulation Engineer in Sunnyvale to define emulation bring-up environments for ASIC and system-level emulation.

You will work with RTL, verification, and silicon teams to validate designs on emulation platforms and develop C++-based testbenches for robust verification. The role requires deep expertise in Verilog/SystemVerilog, C/C++, and scripting, plus a track record in emulation bring-up and debugging.