ASIC DV Intern – Vision & Image-Processing IP

Meta; Sunnyvale (CA); On-site; USD 28,000 - 41,000; Part time

Job summary

Meta in Sunnyvale, CA is seeking a Design Verification intern for the Silicon Accelerators team. You will work with design, verification, and methodology engineers to verify vision and image-processing IP, write test benches, plan tests, and track down bugs in both the design and the test environment.

This internship offers production-level DV experience and a path to full-time as a University Grad Design Verification Engineer, requiring a Master’s in Electrical or Computer Engineering,

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with digital logic design concepts (gates, flops, FSMs, timing)
• Experience with Verilog or SystemVerilog in coursework or projects
• Programming in an OO language (SystemVerilog, C++, Python or Java)
• Python scripting experience
• Ability to obtain work authorization in the United States
• Interest in returning to a full-time degree program after internship
• Exposure to UVM or class-based verification methodology
• Familiarity with verification concepts (constrained-random, coverage, assertions, scoreboarding)
• Projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration
• Hands-on RTL simulation and waveform debugging
• Knowledge of data structures and algorithms
• Completed digital design or verification project such as processor, memory controller, bus/interface, or FPGA design
• Strong debugging instincts and communication

Responsibilities

• Write test benches and verification environments.
• Plan, run, and analyze tests; track down bugs in design and test environment.
• Collaborate with design, verification, and methodology engineers to verify vision/IP.
• Gain production-level DV experience and contribute to standard DV flow.
• Demonstrate strong debugging instincts and clear communication.

Skills

Verilog/SystemVerilog

Python

C++

Debugging

Waveform debugging

Strong communication

Data structures

Constrained-random stimulus

Image processing knowledge

UVM familiarity

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

VCS

Xcelium

Questa

Verilator

RTL simulators

Job description

Meta in Sunnyvale, CA is seeking a Design Verification intern for the Silicon Accelerators team. You will work with design, verification, and methodology engineers to verify vision and image-processing IP, write test benches, plan tests, and track down bugs in both the design and the test environment.

This internship offers production-level DV experience and a path to full-time as a University Grad Design Verification Engineer, requiring a Master’s in Electrical or Computer Engineering,