Verification Engineer Intern

VisLab (an Ambarella Inc. company); Kentucky; On-site; USD 17,000 - 28,000; Full time

Job summary

Ambarella offers internship opportunities in AI Vision Processors for edge applications near completion of a master's degree. Interns will work on designing and verifying VLSI blocks, test benches, and RTL logic for embedded vision accelerators.

Responsibilities include creating test benches, generating tests, and building tools to stimulate and analyze simulations. Proficiency in Verilog/SystemVerilog/UVM and languages like C/C++, Python or assembly is expected with strong time-management and

Qualifications

• Pursuing master's degree in a relevant field.
• Experience with Verilog, SystemVerilog, UVM, C/C++, Python or assembly.
• Ability to deliver assignments on time and present work.

Responsibilities

• Develop test benches (or parts thereof), write and debug tests and RTL logic.
• Write Random Test Generators to automatically and intelligently generate the tests.
• Write coverage monitors, checkers, assertions and collect statistics.
• Create tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.

Skills

VLSI design

Programming

Computer architecture

Education

Master's degree in progress

Tools

Verilog

SystemVerilog

UVM

C

C++

Perl

Python

Assembly

Job description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Ambarella has some exciting internship opportunities for self-motivated and creative students near completion of their master's degree. We are looking for talented engineers who possess a strong interest in VLSI design, programming and computer architecture.

Ambarella designs complex SoCs which include custom DSP and computer vision blocks, CPUs and co-processors. Some example responsibilities will include:

• Develop test benches (or parts thereof), write and debug tests and RTL logic.
• Write Random Test Generators to automatically and intelligently generate the tests.
• Write coverage monitors, checkers, assertions and collect statistics.
• Create tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.

The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be able to pick up missing skills quickly, deliver their assignments on time, and present their work at the end of the program.