ASIC Engineering Intern, Design Verification (Silicon Engineering)

Meta; Sunnyvale (CA); On-site; USD 28,000 - 41,000; Part time

Job summary

Meta in Sunnyvale, CA is seeking a Design Verification intern for the Silicon Accelerators team. You will work with design, verification, and methodology engineers to verify vision and image-processing IP, write test benches, plan tests, and track down bugs in both the design and the test environment.

This internship offers production-level DV experience and a path to full-time as a University Grad Design Verification Engineer, requiring a Master’s in Electrical or Computer Engineering,

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with digital logic design concepts (gates, flops, FSMs, timing)
• Experience with Verilog or SystemVerilog in coursework or projects
• Programming in an OO language (SystemVerilog, C++, Python or Java)
• Python scripting experience
• Ability to obtain work authorization in the United States
• Interest in returning to a full-time degree program after internship
• Exposure to UVM or class-based verification methodology
• Familiarity with verification concepts (constrained-random, coverage, assertions, scoreboarding)
• Projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration
• Hands-on RTL simulation and waveform debugging
• Knowledge of data structures and algorithms
• Completed digital design or verification project such as processor, memory controller, bus/interface, or FPGA design
• Strong debugging instincts and communication

Responsibilities

• Write test benches and verification environments.
• Plan, run, and analyze tests; track down bugs in design and test environment.
• Collaborate with design, verification, and methodology engineers to verify vision/IP.
• Gain production-level DV experience and contribute to standard DV flow.
• Demonstrate strong debugging instincts and clear communication.

Skills

Verilog/SystemVerilog

Python

C++

Debugging

Waveform debugging

Strong communication

Data structures

Constrained-random stimulus

Image processing knowledge

UVM familiarity

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

VCS

Xcelium

Questa

Verilator

RTL simulators

Job description

We are a team of engineers building the silicon IP that powers Augmented Reality (AR) glasses. Our focus is digital design for computer vision and image signal processing: high-performance, low-power hardware that fits into the tight power and space budget of a pair of eyeglasses. Our IP ships in several chips, and our roadmap covers products that will reach the market years from now.

Meta is looking for a Design Verification intern to join our Silicon Accelerators team. You'll work with design, verification, and methodology engineers to verify vision and image-processing IP. You'll write test benches, plan and run tests, and track down bugs in both the design and the test environment. We're looking for someone who likes breaking things and figuring out why they broke. The internship is meant to give you real, production-level DV experience so you're ready to join full-time as a University Grad Design Verification Engineer.

Requirements

• Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• Coursework or project experience in digital logic design: logic gates, flip-flops, finite state machines, timing, and clock domains
• Experience with Verilog or SystemVerilog through coursework, labs, or projects
• Programming experience in an object-oriented language (e.g., SystemVerilog classes, C++, Python, or Java)
• Scripting experience in Python
• Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
• Intent to return to full-time degree program after completion of the internship
• Exposure to UVM (Universal Verification Methodology) or another class-based verification methodology
• Familiarity with verification concepts such as constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding
• Coursework or projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration
• Hands-on experience with an RTL simulator (e.g., VCS, Xcelium, Questa, or Verilator) and waveform debugging
• Knowledge of data structures and algorithms
• A completed digital design or verification project, such as a processor, memory controller, bus or communication interface, or FPGA design
• Strong debugging instincts, curiosity, and clear communication