ASIC DMA Design Engineer for Neural Engine

Anysilicon; Sunnyvale (CA); Hybrid; USD 110,000 - 170,000; Full time

Job summary

Apple's Silicon Engineering Group seeks an ASIC Design Engineer on the ANE DMA Design team to contribute to high‑performance DMA engines for on‑device AI workloads. You will collaborate with architecture and verification teams throughout the design cycle.

Responsibilities include designing DMA subsystems from microarchitecture to tapeout and writing RTL for synthesis, timing, and power. Front‑end tasks such as synthesis, timing closure, linting, and checks are included.

Qualifications

• Familiarity with Verilog/SystemVerilog and digital design fundamentals.
• Exposure to AMBA (AXI, AHB, APB) protocols.
• Understanding of SoC memory systems and data movement.
• Background in high-bandwidth domains such as networking, image processing, or AI/ML.
• Familiarity with scripting for design automation (Python, Perl, Tcl).
• Strong technical writing and proactive design-review communication.

Responsibilities

• Design DMA subsystem blocks from microarchitecture specification through tapeout.
• Write RTL for correct synthesis, clean timing, and low power.
• Execute front-end tasks: synthesis, timing closure, area/power analysis, linting, and equivalence checks.
• Collaborate with architecture and verification teams to understand requirements and refine specs.
• Review test plans and debug failures with design verification teams.

Skills

Verilog/SystemVerilog

AMBA protocols

SoC memory/ data movement

High bandwidth domains

Scripting (Python/Perl/Tcl)

Technical writing & reviews

Education

Bachelor's degree in a relevant field

Job description

Apple's Silicon Engineering Group seeks an ASIC Design Engineer on the ANE DMA Design team to contribute to high‑performance DMA engines for on‑device AI workloads. You will collaborate with architecture and verification teams throughout the design cycle.

Responsibilities include designing DMA subsystems from microarchitecture to tapeout and writing RTL for synthesis, timing, and power. Front‑end tasks such as synthesis, timing closure, linting, and checks are included.