Digital Design Engineer

Credo; San Jose (CA); On-site; USD 80,000 - 133,000; Full time

Job summary

Credo is hiring a Digital Design Engineer in California to lead front-end ASIC design, including complex logic and verification. You will work with Physical Design and Integration teams to enable successful tape-outs and deliver high-quality silicon.

The role emphasizes Verilog/SystemVerilog RTL, RTL verification, and scripting skills. Collaboration with software and systems teams is essential, and eligibility includes a base salary plus bonus/equity and comprehensive benefits.

Qualifications

• Bachelor's degree with 2–7 years of experience or Master's with up to 5 years in Electrical/Electronic or Computer Engineering.
• Understanding of digital logic design and complex synchronous/asynchronous interfaces.
• Knowledge of Verilog/SystemVerilog RTL design from coursework or experience.
• Knowledge of Verilog verification through coursework or projects.
• Knowledge of synthesis and static timing analysis; scripting with Python, Tcl, Perl and shell.

Responsibilities

• Write microarchitecture and design specifications; architect and implement complex logic blocks.
• Integrate IPs from internal/external vendors and support Lint, CDC, synthesis, and ECO.
• Develop functional tests and testbenches; run RTL and gate-level verification/simulations.
• Collaborate with ASIC, DFT, verification, and physical design to achieve tape-out.
• Coordinate with software/firmware teams to validate and debug chip features.

Skills

Digital logic design

Verilog/SystemVerilog

RTL verification

Scripting (Python Tcl Perl shell)

Interface handling (sync/async)

Education

Electrical/Electronic or Computer Engineering degree

Tools

UVM

Verilog/VHDL simulators

IEEE 802.3 Ethernet PHY

Job description

About the role

As a Digital Design Engineer at Credo you are responsible for front-end ASIC design, including design and verification of complex logic blocks, and will collaborate with Physical Design and Integration teams to deliver successful tape-outs.

Base salary range

is $80,000 - $133,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

Why Credo

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

• Bachelor’s degree with two to seven years of experience, or Master’s degree with up to five years of experience in Electrical/Electronic Engineering or Computer Engineering.
• Understanding of digital logic design and knowledge of handling complex synchronous and asynchronous interfaces.
• Knowledge of Verilog/SystemVerilog RTL design, through relevant experience or coursework projects.
• Knowledge of Verilog verification, through relevant experience or coursework projects.
• Knowledge of synthesis and static timing analysis, and of scripting languages such as Python, Tcl, Perl, and shell.

Preferred Qualifications

• Knowledge of UVM.
• Knowledge of the IEEE 802.3 Ethernet physical layer.

Responsibilities

• Write microarchitecture and/or design specifications, and architect, design, implement, and debug complex logic blocks.
• Understand and integrate complex IPs from internal and external IP vendors, and support front-end integration activities such as Lint, CDC, synthesis, and ECO.
• Develop functional tests and testbenches, and run functional RTL and gate-level verification and simulations.
• Work with ASIC design and verification, DFT, and physical design engineers to achieve a successful tape-out.
• Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product, and bring up, validate, and debug functional features in the chip.

About Credo

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI.

Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, gender identity, sexual orientation, pregnancy, marital status, national origin, ethnicity, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [e-mail].

Salary

80000 - 133000 USD (yearly)