Silicon Design Manager, RTL Machine Learning, Accelerator Design

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google is recruiting a Silicon Design Manager in Sunnyvale to shape the future of AI/ML hardware acceleration for TPUs. You will drive high-performance, low-power silicon, collaborating with architects, software teams, and cross-functional groups to enable clocking, power management, and architectural feasibility.

You will guide a team of RTL Design Engineers, define timing goals, and ensure physical design closure while pushing innovation in TPU architectures used across Google's AI platforms.

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent practical experience.
• 10 years of experience with chip design, ASIC digital design and SystemVerilog.
• 8 years in computer architecture and RTL.
• 3 years in people management and developing employees.

Responsibilities

• Lead RTL design engineers on IP development for Compute Cores.
• Provide technical leadership, model best design practices and review designs.
• Be primary contact for design activities, architecture estimation and power/performance trade-offs.
• Collaborate with Verification, DFT, Physical Design, and Software teams throughout the cycle.
• Drive improvements in design methodologies and quality controls.

Skills

Chip Design

ASIC Digital Design

SystemVerilog

People management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

DFT

Verification

Synthesis

STA

Physical Design

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Knowledge of high performance and low-power design techniques.
• Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Silicon Design Manager, you will develop high-performance and low-power hardware to enable continuous innovations in the Tensor Processing Unit (TPUs). In this role, you will work with Architects to drive architectural feasibility, establish timing design goals, and explore trade-offs for physical design closure. You will also work with Software teams to understand and implement clocking and power management requirements.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .