Embedded Systems Engineer, High Speed DSP

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking an experienced engineer in Sunnyvale to help shape TPU firmware for AI silicon. You will lead low‑level firmware and DSP control loops powering high‑speed physical‑layer interfaces and digital transceivers, aligning with AI infrastructure needs.

You will collaborate across TPU Systems, Networking Software, and HPC teams to ensure robust firmware deployment, verification, and silicon‑software co‑design for scalable AI workloads.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 10 years of industry experience in embedded systems/firmware, communication systems engineering, or DSP development.
• Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.

Responsibilities

• Define the long‑term firmware roadmap and hardware‑software partitioning for physical‑layer interfaces, determining the optimal balance between hardware‑fixed logic and programmable firmware.
• Architect advanced in‑situ monitoring systems and firmware‑driven diagnostics to track physical‑layer link health, BER trends, and channel quality across millions of ports in real‑time.
• Design, model, and implement bare‑metal or RTOS firmware to control high‑speed transceivers, managing real‑time adaptive loops, clock and data recovery (CDR), and physical‑layer calibration.
• Partner with TPU Systems, Networking Software, and HPC teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
• Identify and de‑risk hardware‑software interface bottlenecks (register maps, driver latencies, boot sequencing) that impact Google's AI infrastructure.

Skills

Embedded systems

Firmware development

C/C++

DSP

High-speed PHY

Digital transceivers

Communication systems

Wireless comms

Channel modeling

Noise mitigation

Education

Bachelor's degree

Master's degree

PhD

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Haifa, Israel; Tel Aviv, Israel.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
• Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
• Track record defining firmware framework specifications, register maps, and Silicon Life-cycle Management telemetry for high-volume networking or AI silicon.
• Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

In this role, for High‑Speed DSP, you will architect and define the low‑level firmware and control loops powering Google's physical‑layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware‑software co‑design, and real‑time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link‑telemetry frameworks. Your work will directly bridge the gap between high‑performance hardware pipelines and Google’s AI infrastructure, transforming complex communication systems theory into reliable, real‑time silicon execution.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google .

Responsibilities

• Define the long‑term firmware roadmap and hardware‑software partitioning for physical‑layer interfaces, determining the optimal balance between hardware‑fixed logic and programmable firmware.
• Architect advanced "in-situ" monitoring systems and firmware‑driven diagnostics to track physical‑layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real‑time.
• Design, model, and implement bare‑metal or RTOS firmware to control high‑speed transceivers, managing real‑time adaptive loops, clock and data recovery (CDR), and physical‑layer calibration.
• Partner with TPU Systems, Networking Software, and High‑Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
• Identify and de‑risk hardware‑software interface bottlenecks (e.g., register maps, driver latencies, and boot‑up sequencing) that impact Google's AI infrastructure.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .