ASIC Design Manager

Actalent

United States

Hybrid

USD 175,000 - 277,000

Full time

8 days ago

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Hybrid work model

Job summary

Tektronix in Littleton, CO is seeking an ASIC Design Manager to lead and grow its digital ASIC design and realization organization. You will oversee the full ASIC flow from architecture and RTL through IP integration, physical design, signoff, tapeout, and silicon bring-up.

You will mentor engineers, coordinate across engineering teams, influence technology direction, and deliver ASIC solutions enabling next-generation test and measurement innovations.

Qualifications

  • Bachelor's degree or equivalent practical experience in a related technical field.
  • Significant experience developing ASICs or complex digital ICs including design and physical implementation.
  • Experience leading technical projects and mentoring engineers.
  • Strong understanding of digital design methodologies, microarchitecture, and timing analysis.

Responsibilities

  • Lead the digital ASIC design and realization organization.
  • Oversee the complete ASIC flow from architecture to silicon bring-up.
  • Mentor engineers and coordinate work across multidisciplinary teams.
  • Influence technology direction and program execution.
  • Deliver ASIC solutions enabling next-gen test and measurement innovations.

Skills

ASIC design leadership
Verilog/SystemVerilog
RTL development
Physical design
Mentoring engineers
Synthesis & STA
IP integration

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence tools
Synopsys tools
Siemens EDA

Job description

Job Title: ASIC Design Manager Job Description

We are seeking an ASIC Design Manager to lead and grow our digital ASIC design and realization organization. ASICs are at the core of next-generation instrumentation platforms, and this role involves overseeing the execution of the complete ASIC flow, from architecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up.

Responsibilities
  • Lead the digital ASIC design and realization organization.
  • Oversee execution across the complete ASIC flow, including architecture, RTL development, IP integration, physical design, signoff, tapeout, and silicon bring-up.
  • Mentor engineers and coordinate work across multidisciplinary engineering teams.
  • Influence technology direction, engineering methodology, and program execution.
  • Deliver ASIC solutions that enable the next generation of test and measurement innovation.
Essential Skills
  • Bachelors degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience.
  • Significant experience in developing ASICs or complex digital integrated circuits, including digital design and physical implementation.
  • Experience leading technical projects and mentoring engineers.
  • Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.
  • Experience with physical design and implementation, including floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.
  • Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.
  • Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.
  • Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production.
Additional Skills & Qualifications
  • Strong communication, collaboration, organizational, and problem-solving skills.
  • Ability to work effectively across engineering, product, and program-management teams.
  • Experience with FPGA.
Work Environment

This role requires at least 2 days in the office, providing the opportunity to collaborate directly with a talented engineering team responsible for strategic silicon development.

Job Type & Location

This is a Permanent position based out of Littleton, CO.

Pay and Benefits

The pay range for this position is $175000.00 - $276500.00/yr.

Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.

Tektronix, a wholly owned subsidiary of Ralliant Corporation, is a place where people are challenged to explore the boundaries of whats possible, bringing the digital future one step closer every day. Through precision-engineered measurement solutions, we work with our customers to eliminate the barriers between inspiration and realization of world-changing technologies. We believe that cultivating a deeper sense of loyalty and belonging is key to how we attract and retain our best people. This reality inspires our Inclusion & Diversity vision, We Are More Together, and guides our approach as we all work toward creating great places where our teams work and thrive. Realize your true potential at Tektronix join us in revolutionizing a better tomorrow!

Job Type & Location

This is a Permanent position based out of Littleton, CO.

Application Deadline

This position is anticipated to close on Nov 3, 2026.

Workplace Type

This is a hybrid position in Littleton,CO.

The company is an equal opportunity employer and will consider all applications withoutregard to race, sex, age, color, religion, national origin, veteran status, disability,sexual orientation, gender identity, genetic information or any characteristic protectedby law.

If you would like to request a reasonable accommodation, such as the modification oradjustment of the job application process or interviewing process due to a disability,please email actalentaccommodation@actalentservices.com for other accommodation options.

San Francisco Fair Chance Ordinance:Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in thecity and county of San Francisco, we will consider for employment qualified applicantswith arrest and conviction records.

Massachusetts Lie Detector:It is unlawful in Massachusetts to require or administer a lie detector test as acondition of employment or continued employment. An employer who violates this lawshall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI):We may use Artificial Intelligence (AI) to support parts of our hiring process,including sourcing, screening, and evaluating candidates. AI helps assess applicationsand qualifications, but final decisions are made by our hiring team. By applying, youacknowledge and agree that your application may be reviewed using AI tools.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

ASIC Design Manager
ASIC Design Manager

Actalent • Littleton (CO)

Hybrid
USD 175,000 - 277,000
ASIC Design Manager
ASIC Design Manager

Ralliant • Boulder (CO)

Hybrid
USD 149,000 - 277,000
ASIC Verification Engineer
ASIC Verification Engineer

Talentify • Town of Pittsford (NY)

On-site
USD 99,000 - 152,000
Medical, dental & vision
401(k) Retirement Plan – Pre-tax and R
Health Savings Account (HSA)
+5
ASIC Design Manager Tektronix Boulder, CO, United States + 1 more Posted 7 hours ago
ASIC Design Manager Tektronix Boulder, CO, United States + 1 more Posted 7 hours ago

Ralliant • Louisville (CO)

On-site
USD 149,000 - 277,000
ASIC Design Manager
ASIC Design Manager

Tektronix, Inc. • Boulder (CO)

On-site
USD 149,000 - 277,000
FPGA Engineer
FPGA Engineer

Actalent • Newtown (PA)

Hybrid
USD 76,000 - 92,000
Senior ASIC Technical Lead
Senior ASIC Technical Lead

Randstad USA • Agoura Hills (CA)

On-site
USD 240,000 - 280,000
Profit sharing
Stock options
Bonus
ASIC Engineering Technical Leader
ASIC Engineering Technical Leader

Capgemini • San Jose (CA)

On-site
USD 57,000 - 90,000
Medical benefits
Dental benefits
Vision benefits
+1
Dsp Engineer
Dsp Engineer

Actalent • Broomfield (CO)

On-site
USD 100,000 - 200,000
ESPP discount purchase shares at 15%
401k company match at 100% of first 6%
RSU grants potential
Analog Design Engineer (TERADYNE, Agoura Hills, CA)
Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 128,000 - 204,000
medical
dental
vision
+5