ASIC Design Manager

Tektronix, Inc.; Boulder (CO); On-site; USD 149,000 - 277,000; Full time

Job summary

Tektronix seeks an ASIC Design Manager to lead our digital ASIC design and realization team across Boulder/CO, Louisville/CO or Beaverton/OR. You will own the end-to-end digital ASIC flow, including microarchitecture, RTL development, IP selection, synthesis, floorplanning, timing closure, tapeout, and silicon bring-up.

You will mentor engineers, guide IP and subsystem design, manage schedules and risk, and collaborate with product architects and external partners to meet performance targets and

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Significant experience developing ASICs or complex digital ICs, including digital design and physical implementation activities.
• Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary teams.
• Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.
• Experience with physical design and implementation, including floorplanning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.
• Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.
• Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.
• Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release.

Responsibilities

• Lead digital ASIC design, verification, and physical design teams; establish priorities and mentor engineers.
• Own end-to-end digital ASIC development flow from architecture to tapeout, including IP selection and integration.
• Set technical direction for digital IP, subsystems, full-chip integration, and physical implementation.
• Drive physical design planning and execution including floorplanning, power-grid, clock distribution, and routing optimization.
• Coordinate with product and system architects to translate requirements into ASIC specs and performance targets.
• Oversee signoff activities: static timing analysis, signal integrity, power integrity, IR-drop, electromigration, DRC/LVS, and tapeout readiness reviews.
• Collaborate with packaging, foundry, and external design-services teams for die planning and package integration.
• Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestones, and risk mitigation.
• Recruit and retain engineering talent, manage contractors and external vendors as needed.
• Contribute to technical reviews and critical design work when needed to accelerate delivery.

Skills

Digital design

RTL design

SystemVerilog

Verilog RTL

IP integration

Synthesis

Constraints development

Static timing analysis

Timing closure

DFT

Leadership

Education

Bachelor's degree in Electrical Engineering or Computer Engineering or related technical discipline

Master’s or doctoral degree in Electrical/Computer Engineering or related field

Tools

Cadence

Synopsys

Siemens EDA

Job description

Boulder, CO, United StatesASIC Design ManagerLocation: Louisville, CO or Beaverton, OROrganization: ASIC Development Group, TektronixOverviewAt Tektronix, we believe innovation starts with our customers. For more than eighty years, we have delivered industry-leading test and measurement solutions that help engineers solve complex challenges around the world. Our engineering culture is collaborative, technically rigorous, and committed to innovation, continuous learning, and professional growth.We are seeking an ASIC Design Manager to lead and grow our digital ASIC design and realization organization. ASICs are at the core of Tektronix’s next-generation instrumentation platforms, and this role is responsible for execution across the complete ASIC flow, from architecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up.This hands-on leadership role combines people management, vendor relations, technical direction, and project execution. You will lead engineers responsible for digital design, verification, and physical implementation while remaining engaged in critical architecture, implementation, timing closure, power integrity, and signoff decisions. The successful candidate will bring strong experience in ASIC development and the ability to guide a multidisciplinary team through complex technical and program challenges.Key ResponsibilitiesLead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers; establish clear priorities, support career growth, and foster a collaborative engineering culture.Own the end-to-end digital ASIC development flow, including microarchitecture, RTL development, IP selection and integration, synthesis, constraints development, floorplanning, clock-tree synthesis, place-and-route, timing closure, and tapeout.Set technical direction for digital IP, subsystem design, full-chip integration, and physical implementation, balancing performance, power, area, reliability, reuse, cost, and schedule.Drive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure.Have knowledge of digital-on-top development flows for mixed-signal designs.Oversee signoff activities, including static timing analysis, signal integrity, power integrity, IR-drop analysis, electromigration analysis, formal equivalence, DRC, LVS, and tapeout-readiness reviews.Partner with product and system architects to translate product requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets.Coordinate execution across functional UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams.Collaborate with package design and process-technology teams on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration.Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestone tracking, and risk mitigation.Drive design quality through disciplined methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria.Improve design flows, automation, and engineering practices to increase productivity, quality, reuse, and schedule predictability.Support silicon bring-up, characterization, post-silicon debug, and production-readiness activities.Recruit and retain engineering talent, and manage contractors, external design-service providers, IP vendors, and other technical partners as needed.Contribute directly to technical reviews and critical design or implementation work when it helps accelerate the team or reduce project risk.A Typical Day Might IncludeReviewing a microarchitecture proposal or RTL implementation and helping resolve an interface, performance, or integration issue.Leading a floorplan or implementation review and evaluating tradeoffs among timing, power, congestion, area, and reliability.Working with physical design engineers to resolve timing, IR-drop, electromigration, signal-integrity, or physical-verification issues before tapeout.Collaborating with architects, packaging engineers, and foundry partners to refine system partitioning and die-to-package integration.Meeting with IP and design services vendors to discuss possible engagements.Reviewing project status with program management, addressing technical risks, and adjusting priorities or resources.Coaching an engineer, conducting a technical review, or interviewing a candidate.Minimum QualificationsBachelor’s degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience.Significant experience developing ASICs or complex digital integrated circuits, including digital design and physical implementation activities.Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary engineering teams.Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis.Experience with physical design and implementation, including several of the following: floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff.Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs.Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers.Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release.Strong communication, collaboration, organizational, and problem-solving skills, with the ability to work effectively across engineering, product, and program-management teams.Preferred QualificationsExperience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning.Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field.Experience leading end-to-end digital ASIC or SoC implementation through tapeout.Experience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications.Experience with multi-mode, multi-corner timing analysis; signal-integrity analysis; IR-drop and electromigration verification; or other physical signoff methodologies.Experience optimizing designs for performance, power, area, yield, reliability, and manufacturability.Familiarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or other advanced packaging technologies.Experience with FPGA prototyping, emulation, or other pre-silicon validation methods.Experience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers.Experience improving ASIC development methodologies, automation, and team execution practices.Why Join Tektronix?This role offers the opportunity to shape the future of Tektronix instrumentation platforms while leading a talented engineering team responsible for strategic silicon development. You will influence technology direction, engineering methodology, and program execution while helping deliver ASIC solutions that enable the next generation of test and measurement innovation.#LI-RG1Ralliant Corporation OverviewRalliant, originally part of Fortive, now stands as a bold, independent public company driving innovation at the forefront of precision technology. With a global footprint and a legacy of excellence, we empower engineers to bring next-generation breakthroughs to life — faster, smarter, and more reliably. Our high-performance instruments, sensors, and subsystems fuel mission-critical advancements across industries, enabling real-world impact where it matters most. At Ralliant we're building the future, together with those driven to push boundaries, solve complex problems, and leave a lasting mark on the world.About TektronixTektronix, a wholly owned subsidiary of Ralliant Corporation, is a place where people are challenged to explore the boundaries of what’s possible, bringing the digital future one step closer every day. Through precision-engineered measurement solutions, we work with our customers to eliminate the barriers between inspiration and realization of world-changing technologies. We believe that cultivating a deeper sense of loyalty and belonging is key to how we attract and retain our best people. This reality inspires our Inclusion & Diversity vision, We Are More Together, and guides our approach as we all work toward creating great places where our teams work and thrive. Realize your true potential at Tektronix – join us in revolutionizing a better tomorrow!We Are an Equal Opportunity Employer. Ralliant Corporation and all Ralliant Companies are proud to be equal opportunity employers. We value and encourage diversity and solicit applications from all qualified applicants without regard to race, color, national origin, religion, sex, age, marital status, disability, veteran status, sexual orientation, gender identity or expression, or other characteristics protected by law. Ralliant and all Ralliant Companies are also committed to providing reasonable accommodations for applicants with disabilities. Individuals who need a reasonable accommodation because of a disability for any part of the employment application process, please contact us at [e-mail] RangeThe salary range for this position (in local currency) is 148900.00-276500.00Is this role subject to ITAR?The essential duties of this position require adherence to U.S. Government export control regulations. Accordingly, candidates must either be U.S. Persons (i.e., U.S. citizens, U.S. lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3)) or be prepared to collaborate with the company in securing the necessary U.S. government export authorizations. While the company encourages all interested applicants to apply, please be aware that ongoing employment is dependent upon obtaining the appropriate government export authorizations.