Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne

Agoura Hills (CA)

On-site

USD 128,000 - 204,000

Full time

2 days ago
Be an early applicant
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Job summary

Teradyne's Semiconductor Test Division in Agoura Hills, CA is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).

Candidates will design from spec to transistor-level, validate with Cadence tools, and collaborate across AI-enabled design teams to accelerate semiconductor innovation.

Strong background in CMOS, FinFET, and high-frequency IC design, plus scripting in Python or SKILL, is highly valued.

Qualifications

  • MSEE or higher preferred with 2+ years of mixed-signal IC design and characterization.
  • ],
  • job_responsibilities_description':['Design and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.','Validate and integrate designs using Cadence EDA tools across PVT corners, supporting layout and ASIC integration.','Participate in silicon characterization, debug, validation, and production test activities.','Develop automation, scripting, and AI-assisted workflows to improve design productivity, verification, and data analysis.','Collaborate across design, validation, test, and EDA teams to advance AI-enabled IC design methodologies.'],
  • CoT_job_summary_short
  • job_summary_short
  • contract_type
  • location_type
  • remote_scope
  • perks
  • stated_min
  • stated_max
  • stated_absolute
  • salary_estimation_cot
  • estimated_low
  • estimated_medium
  • estimated_high
  • currency
  • frequency
  • bonus
  • tax
  • application_email
  • job_end_date
  • contact_person
  • hiring_department_name

Education

MSEE or higher

Tools

Cadence EDA
Python scripting
Ocean scripting
SKILL scripting

Job description

Select how often (in days) to receive an alert:

Date: Oct 12, 2026

Location: Agoura Hills, CA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respect their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE). The ideal candidate will have experience in CMOS circuit design and successful ASIC tape‑outs, along with strong analytical, problem‑solving, and communication skills. This role offers the opportunity to collaborate across multidisciplinary teams while leveraging AI‑powered tools, automation, and data‑driven methodologies to accelerate semiconductor innovation. A passion for emerging technologies, continuous learning, and technical excellence is highly valued.

Responsibilities include:

  • Design and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
  • Validate and integrate designs using Cadence EDA tools across PVT corners, while supporting layout and ASIC integration.
  • Participate in silicon characterization, debug, validation, and production test activities.
  • Develop automation, scripting, and AI‑assisted workflows to improve design productivity, verification, and data analysis.
  • Collaborate across design, validation, test, and EDA teams to advance AI‑enabled IC design methodologies.
All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. Ifyou’reready to join usinthis mission, take a closer look at theminimumcriteria for the position.

  • MSEE or higher preferred, with 2+ years of experience in mixed-signal IC design and characterization; FinFET (16nm and below) experience is a plus.
  • Strong knowledge of high-frequency analog/mixed-signal IC design, including PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, and CML designs.
  • Solid understanding of CMOS device physics, semiconductor processes, PDKs, thermal effects, and electromagnetic principles.
  • Experience throughout the IC development lifecycle, including silicon characterization and laboratory measurements.
  • Familiarity with AI/ML techniques, generative AI, and large-scale data analysis for semiconductor design, validation, and test applications.
  • Proficiency in scripting languages (Python/SKILL/Ocean) for automation and data analysis; Verilog/Verilog-A experience is a plus.

We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.

Compensation

The base salary range for this role is $127,500 to $204,100. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits
  • medical
  • dental
  • vision
  • Flexible Spending Accounts
  • retirement savings plans
  • life and disability insurance
  • paid vacation & holidays
  • tuition assistance programs
  • and more

Please click here to see details.

#LI-MD1

Nearest Major Market

Los Angeles

Job Segment

Data Analyst, Thermal Engineering, Design Engineer, Electrical Engineering, Manufacturing Engineer, Data, Engineering

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Sr. Analog Design Engineer (TERADYNE, Agoura Hills, CA)
Sr. Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 155,000 - 248,000
Health benefits
Discretionary bonus plan
Senior Analog Design Engineer (Teradyne, Agoura Hills, CA))
Senior Analog Design Engineer (Teradyne, Agoura Hills, CA))

Teradyne • Agoura Hills (CA)

On-site
USD 119,000 - 191,000
Health insurance
Dental insurance
Vision coverage
+3
Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)
Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)

Teradyne • North Reading (MA)

On-site
USD 192,000 - 308,000
Medical insurance
Dental insurance
Vision care
+2
Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)
Senior RTL Digital Design Engineer (TERADYNE, North Reading, MA)

Teradyne • Reading (MA), Northern (KY)

On-site
USD 192,000 - 308,000
Medical benefits
Dental insurance
Vision insurance
+5
Sr. Hardware Engineer (Compute Test, Agoura Hills)
Sr. Hardware Engineer (Compute Test, Agoura Hills)

Teradyne • Agoura Hills (CA)

On-site
USD 141,000 - 226,000
Medical insurance
Dental insurance
Vision insurance
+3
Senior ASIC Chip Lead / Project Lead
Senior ASIC Chip Lead / Project Lead

Teradyne • Agoura Hills (CA)

On-site
USD 192,000 - 308,000
Medical
Dental
Vision
+5
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 192,000 - 308,000
medical
dental
vision
+6
Mechanical Engineer (Teradyne, Agoura Hills, CA)
Mechanical Engineer (Teradyne, Agoura Hills, CA)

Teradyne • Agoura Hills (CA), Northern (KY)

On-site
USD 122,000 - 195,000
Health insurance
Retirement plans
Tuition assistance
Software Engineer
Software Engineer

Teradyne • Agoura Hills (CA)

On-site
USD 120,000 - 180,000
Health benefits
Tuition assistance
Paid time off
Senior Mechanical Engineer (Teradyne, Agoura Hills, CA)
Senior Mechanical Engineer (Teradyne, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 154,000 - 246,000
Medical insurance
Dental insurance
Vision insurance
+1